linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author	Files	Lines
2021-06-27	clk: ingenic: Add support for the JZ4760	Paul Cercueil	4	-0/+441
2021-06-27	clk: ingenic: Support overriding PLLs M/N/OD calc algorithm	Paul Cercueil	2	-13/+30
2021-06-27	clk: ingenic: Remove pll_info.no_bypass_bit	Paul Cercueil	3	-8/+6
2021-06-27	clk: ingenic: Read bypass register only when there is one	Paul Cercueil	1	-8/+11
2021-06-27	clk: Support bypassing dividers	Paul Cercueil	5	-29/+42
2020-12-19	clk: ingenic: Fix divider calculation with div tables	Paul Cercueil	1	-4/+10
2020-10-13	clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate	Paul Cercueil	1	-0/+2
2020-10-13	clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT	Paul Cercueil	1	-7/+7
2020-10-13	clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL	Paul Cercueil	1	-2/+7
2020-10-13	clk: ingenic: Use readl_poll_timeout instead of custom loop	Paul Cercueil	1	-26/+29
2020-10-13	clk: ingenic: Use to_clk_info() macro for all clocks	Paul Cercueil	1	-39/+15
2020-07-27	clk: X1000: Add support for calculat REFCLK of USB PHY.	周琰杰 (Zhou Yanjie)	1	-1/+83
2020-07-27	clk: JZ4780: Reformat the code to align it.	周琰杰 (Zhou Yanjie)	1	-45/+45
2020-07-27	clk: JZ4780: Add functions for enable and disable USB PHY.	周琰杰 (Zhou Yanjie)	1	-30/+35
2020-07-27	clk: Ingenic: Add RTC related clocks for Ingenic SoCs.	周琰杰 (Zhou Yanjie)	3	-0/+38
2020-05-28	clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused	Stephen Boyd	1	-1/+1
2020-05-28	clk: X1000: Add FIXDIV for SSI clock of X1000.	周琰杰 (Zhou Yanjie)	1	-6/+111
2020-05-28	clk: Ingenic: Add CGU driver for X1830.	周琰杰 (Zhou Yanjie)	3	-0/+459
2020-05-28	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	周琰杰 (Zhou Yanjie)	7	-4/+41
2020-05-28	clk: Ingenic: Remove unnecessary spinlock when reading registers.	周琰杰 (Zhou Yanjie)	1	-11/+1
2020-03-20	clk: ingenic/TCU: Fix round_rate returning error	Paul Cercueil	1	-1/+1
2020-03-20	clk: ingenic/jz4770: Exit with error if CGU init failed	Paul Cercueil	1	-1/+3
2020-03-20	clk: JZ4780: Add function for enable the second core.	周琰杰 (Zhou Yanjie)	1	-5/+50
2020-03-20	clk: Ingenic: Add support for TCU of X1000.	周琰杰 (Zhou Yanjie)	1	-0/+8
2019-11-27	Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...	Stephen Boyd	3	-1/+286
2019-11-22	clk: ingenic: Allow drivers to be built with COMPILE_TEST	Stephen Boyd	1	-1/+1
2019-11-13	clk: Ingenic: Add CGU driver for X1000.	Zhou Yanjie	3	-0/+285
2019-11-08	drivers/clk: convert VL struct to struct_size	Stephen Kitt	1	-2/+1
2019-09-22	Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux	Linus Torvalds	4	-1/+490
2019-08-12	clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro	Paul Cercueil	4	-4/+4
2019-08-08	clk: jz4740: Add TCU clock	Paul Cercueil	1	-0/+6
2019-08-08	clk: ingenic: Add driver for the TCU clocks	Paul Cercueil	3	-1/+484
2019-08-07	clk: ingenic/jz4740: Fix "pll half" divider not read/written properly	Paul Cercueil	1	-1/+8
2019-07-17	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	9	-128/+192
2019-06-25	clk: ingenic: Remove unused functions	Paul Cercueil	1	-73/+0
2019-06-25	clk: ingenic: Handle setting the Low-Power Mode bit	Paul Cercueil	7	-32/+69
2019-06-25	clk: ingenic: Add missing header in cgu.h	Paul Cercueil	1	-0/+1
2019-06-07	clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly	Paul Cercueil	1	-1/+8
2019-06-07	clk: ingenic/jz4725b: Fix incorrect dividers for main clocks	Paul Cercueil	1	-5/+24
2019-06-07	clk: ingenic/jz4770: Fix incorrect dividers for main clocks	Paul Cercueil	1	-6/+28
2019-06-07	clk: ingenic/jz4740: Fix incorrect dividers for main clocks	Paul Cercueil	1	-5/+24
2019-06-07	clk: ingenic: Add support for divider tables	Paul Cercueil	2	-6/+38
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner	4	-40/+4
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	2	-0/+2
2019-05-15	clk: Remove io.h from clk-provider.h	Stephen Boyd	4	-0/+4
2019-04-11	clk: ingenic: jz4725b: Add UDC PHY clock	Paul Cercueil	1	-0/+6
2019-02-26	clk: ingenic: Remove set but not used variable 'enable'	YueHaibing	1	-2/+1
2019-02-22	clk: ingenic: Fix doc of ingenic_cgu_div_info	Paul Cercueil	1	-1/+1
2019-02-22	clk: ingenic: Fix round_rate misbehaving with non-integer dividers	Paul Cercueil	1	-5/+5
2019-02-05	clk: ingenic: jz4740: Fix gating of UDC clock	Paul Cercueil	1	-1/+1