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path: root/drivers/clk/mediatek
AgeCommit message (Expand)AuthorFilesLines
2016-11-08reset: mediatek: Add MT2701 reset driverGravatar Shunli Wang 2-4/+16
2016-11-08clk: mediatek: Add MT2701 clock supportGravatar Shunli Wang 14-5/+1797
2016-10-17clk: mediatek: Add hardware dependencyGravatar Jean Delvare 1-0/+2
2016-09-21clk: mediatek: clk-mt8173: Unmap region obtained by of_iomapGravatar Arvind Yadav 1-1/+3
2016-08-19clk: mediatek: Refine the makefile to support multiple clock driversGravatar James Liao 2-3/+24
2016-08-18clk: mediatek: remove __init from clk registration functionsGravatar James Liao 3-8/+8
2016-05-06clk: mediatek: remove hdmitx_dig_cts from TOP clocksGravatar Philipp Zabel 1-1/+0
2016-05-06clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock outputGravatar Philipp Zabel 1-0/+5
2016-05-06clk: mediatek: make dpi0_sel propagate rate changesGravatar Philipp Zabel 2-3/+18
2016-03-29clk: mediatek: Make reset_control_ops constGravatar Philipp Zabel 1-1/+1
2016-03-02clk: mediatek: Remove CLK_IS_ROOTGravatar Stephen Boyd 1-2/+2
2016-01-29clk: mediatek: Fix memory leak on clock init failGravatar James Liao 1-2/+4
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGravatar Geliang Tang 2-5/+5
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSGravatar James Liao 5-7/+159
2015-10-01clk: mediatek: Add subsystem clocks of MT8173Gravatar James Liao 1-0/+267
2015-10-01clk: mediatek: Fix rate and dependency of MT8173 clocksGravatar James Liao 1-6/+13
2015-10-01clk: mediatek: Add fixed clocks support for Mediatek SoC.Gravatar James Liao 2-0/+40
2015-10-01clk: mediatek: Add __initdata and __init for data and functionsGravatar James Liao 3-10/+11
2015-10-01clk: mediatek: Remove unused code from MT8173.Gravatar James Liao 2-4/+2
2015-10-01clk: mediatek: Removed unused dpi_ck clock from MT8173Gravatar James Liao 1-1/+0
2015-10-01clk: mediatek: add 13mhz clock for MT8173Gravatar Joe.C 1-0/+5
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextGravatar Stephen Boyd 4-2/+6
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportGravatar James Liao 3-6/+42
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsGravatar James Liao 1-2/+2
2015-07-28clk: mediatek: Fix PLL registers setting flowGravatar James Liao 1-9/+12
2015-07-20clk: mediatek: Properly include clk.hGravatar Stephen Boyd 4-2/+6
2015-07-06clk: mediatek: mt8173: Fix enabling of critical clocksGravatar Sascha Hauer 1-5/+21
2015-06-04clk: mediatek: Fix apmixedsys clock registrationGravatar James Liao 2-2/+2
2015-05-19clk: mediatek: Initialize clk_init_dataGravatar Ricky Liang 2-2/+2
2015-05-05clk: mediatek: Add basic clocks for Mediatek MT8173.Gravatar James Liao 2-0/+831
2015-05-05clk: mediatek: Add basic clocks for Mediatek MT8135.Gravatar James Liao 2-0/+645
2015-05-05clk: mediatek: Add reset controller supportGravatar Sascha Hauer 3-0/+108
2015-05-05clk: mediatek: Add initial common clock support for Mediatek SoCs.Gravatar James Liao 6-0/+898