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path:
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drivers
/
clk
/
meson
/
meson8b.h
Age
Commit message (
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Author
Files
Lines
2017-08-04
clk: meson: meson8b: register the built-in reset controller
Martin Blumenstingl
1
-1
/
+8
2017-08-04
clk: meson8b: expose every clock in the bindings
Jerome Brunet
1
-99
/
+4
2017-06-12
clk: meson8b: export the ethernet gate clock
Martin Blumenstingl
1
-1
/
+1
2017-06-12
clk: meson8b: export the USB clocks
Martin Blumenstingl
1
-5
/
+5
2017-06-12
clk: meson8b: export the gate clock for the HW random number generator
Martin Blumenstingl
1
-1
/
+1
2017-06-12
clk: meson8b: export the SDIO clock
Martin Blumenstingl
1
-1
/
+1
2017-06-12
clk: meson8b: export the SAR ADC clocks
Martin Blumenstingl
1
-2
/
+2
2017-03-27
clk: meson8b: add the mplls clocks 0, 1 and 2
Jerome Brunet
1
-1
/
+19
2016-09-01
meson: clk: Add support for clock gates
Alexander Müller
1
-0
/
+5
2016-09-01
clk: meson: Copy meson8b CLKID defines to private header file
Alexander Müller
1
-0
/
+107
2016-09-01
meson: clk: Rename register names according to Amlogic datasheet
Alexander Müller
1
-6
/
+5
2016-09-01
meson: clk: Move register definitions to meson8b.h
Alexander Müller
1
-0
/
+40