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path: root/drivers/clk/pistachio
AgeCommit message (Expand)AuthorFilesLines
2022-02-25clk: pistachio: Declare mux table as const u32[]Gravatar Jonathan Neuschäfer 1-1/+1
2021-08-12clk: pistachio: Make it selectable for generic MIPS kernelGravatar Jiaxun Yang 1-0/+8
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422Gravatar Thomas Gleixner 4-16/+4
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigGravatar Thomas Gleixner 1-0/+1
2018-11-06clk: pistachio: constify clk_ops structuresGravatar Julia Lawall 1-4/+4
2015-08-26clk: pistachio: correct critical clock listGravatar Damien.Horsley 1-5/+14
2015-08-26clk: pistachio: Fix PLL rate calculation in integer modeGravatar Zdenko Pulitika 1-2/+46
2015-08-26clk: pistachio: Fix override of clk-pll settings from boot loaderGravatar Zdenko Pulitika 1-3/+2
2015-08-26clk: pistachio: Fix 32bit integer overflowsGravatar Zdenko Pulitika 2-21/+19
2015-08-24clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Gravatar Stephen Boyd 1-2/+2
2015-07-20clk: pistachio: Include clk.hGravatar Stephen Boyd 1-0/+1
2015-06-04clk: pistachio: Add sanity checks on PLL configurationGravatar Kevin Cernekee 1-4/+79
2015-06-04clk: pistachio: Lock the PLL when enabled upon rate changeGravatar Ezequiel Garcia 1-18/+10
2015-06-04clk: pistachio: Add a pll_lock() helper for clarityGravatar Ezequiel Garcia 1-4/+8
2015-03-31CLK: Pistachio: Register external clock gatesGravatar Andrew Bresticker 1-0/+21
2015-03-31CLK: Pistachio: Register system interface gate clocksGravatar Andrew Bresticker 1-0/+42
2015-03-31CLK: Pistachio: Register peripheral clocksGravatar Andrew Bresticker 1-0/+67
2015-03-31CLK: Pistachio: Register core clocksGravatar Andrew Bresticker 2-0/+200
2015-03-31CLK: Pistachio: Add PLL driverGravatar Andrew Bresticker 3-0/+452
2015-03-31CLK: Add basic infrastructure for Pistachio clocksGravatar Andrew Bresticker 3-0/+265