Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-09-04 | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | 1 | -2/+2 | |
2018-09-28 | clk: renesas: Convert to SPDX identifiers | 1 | -4/+1 | |
2018-02-20 | clk: renesas: r8a7790: Add rwdt clock | 1 | -0/+2 | |
2017-05-24 | clk: renesas: r8a7790: Add new CPG/MSSR driver | 1 | -0/+278 |