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path: root/drivers/clk/renesas/r8a77980-cpg-mssr.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-13clk: renesas: Move RPC core clocksGravatar Geert Uytterhoeven 1-5/+5
2021-11-19clk: renesas: rcar-gen3: Add SDnH clockGravatar Wolfram Sang 1-1/+2
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalGravatar Ulrich Hecht 1-1/+1
2019-04-02clk: renesas: r8a77980: Fix RPC-IF module clock's parentGravatar Sergei Shtylyov 1-1/+1
2019-02-05clk: renesas: r8a77980: Add RPC clocksGravatar Sergei Shtylyov 1-0/+8
2018-09-03clk: renesas: r8a77980: Add CMT clocksGravatar Sergei Shtylyov 1-0/+4
2018-08-27clk: renesas: r8a77980: Add RCLK for watchdog timerGravatar Geert Uytterhoeven 1-0/+4
2018-08-27clk: renesas: r8a77980: Add OSC predivider configuration and clockGravatar Geert Uytterhoeven 1-11/+13
2018-04-16clk: renesas: r8a77980: Correct parent clock of PCIEC0Gravatar Geert Uytterhoeven 1-1/+1
2018-02-20clk: renesas: cpg-mssr: add R8A77980 supportGravatar Sergei Shtylyov 1-0/+227