aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/renesas/r8a77990-cpg-mssr.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-13clk: renesas: Move RPC core clocksGravatar Geert Uytterhoeven 1-4/+2
2022-04-11clk: renesas: r8a77990: Add RPC clocksGravatar Geert Uytterhoeven 1-0/+9
2022-01-24clk: renesas: r8a7799[05]: Add MLP clocksGravatar Nikita Yushchenko 1-0/+1
2021-11-19clk: renesas: rcar-gen3: Add SDnH clockGravatar Wolfram Sang 1-3/+6
2021-03-08clk: renesas: r8a77990: Add DAB clockGravatar Fabrizio Castro 1-0/+1
2020-12-28clk: renesas: r8a77990: Add TMU clocksGravatar Niklas Söderlund 1-0/+5
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalGravatar Ulrich Hecht 1-0/+1
2020-02-10clk: renesas: rcar-gen3: Add CCREE clocksGravatar Geert Uytterhoeven 1-0/+2
2019-06-18clk: renesas: r8a77990: Add CMM clocksGravatar Jacopo Mondi 1-0/+2
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksGravatar Takeshi Kihara 1-9/+9
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACGravatar Takeshi Kihara 1-1/+1
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBGravatar Kazuya Mizuguchi 1-1/+1
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIGravatar Kazuya Mizuguchi 1-1/+1
2019-04-02clk: renesas: r8a77990: Add Z2 clockGravatar Takeshi Kihara 1-0/+1
2018-12-04clk: renesas: r8a77990: Correct parent clock of DUGravatar Takeshi Kihara 1-2/+2
2018-09-25clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGravatar Geert Uytterhoeven 1-2/+2
2018-08-31clk: renesas: r8a77990: Add missing I2C7 clockGravatar Geert Uytterhoeven 1-0/+1
2018-08-27clk: renesas: r8a77990: Correct RCLK handlingGravatar Geert Uytterhoeven 1-2/+10
2018-05-09clk: renesas: cpg-mssr: Add support for R-Car E3Gravatar Yoshihiro Shimoda 1-0/+289