linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author	Files	Lines
2022-06-06	clk: renesas: r9a07g044: Add POEG clock and reset entries	Biju Das	1	-1/+13
2022-06-06	clk: renesas: r9a07g044: Add GPT clock and reset entry	Biju Das	1	-1/+4
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	1	-0/+4
2022-05-05	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	1	-15/+8
2022-05-05	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	1	-4/+2
2022-05-05	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	1	-9/+6
2022-05-05	clk: renesas: r9a07g044: Fix OSTM1 module clock name	Geert Uytterhoeven	1	-1/+1
2022-05-05	clk: renesas: r9a07g044: Add DSI clock and reset entries	Biju Das	1	-1/+16
2022-05-05	clk: renesas: r9a07g044: Add LCDC clock and reset entries	Biju Das	1	-1/+8
2022-05-05	clk: renesas: r9a07g044: Add M4 Clock support	Biju Das	1	-1/+18
2022-05-05	clk: renesas: r9a07g044: Add M3 Clock support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add M1 clock support	Biju Das	1	-1/+10
2022-02-10	clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC	Biju Das	1	-190/+236
2022-01-24	clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3	Lad Prabhakar	1	-2/+2
2021-12-08	clk: renesas: r9a07g044: Add GPU clock and reset entries	Biju Das	1	-0/+9
2021-12-08	clk: renesas: r9a07g044: Add mux and divider for G clock	Biju Das	1	-0/+6
2021-12-08	clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro	Biju Das	1	-2/+2
2021-11-26	clk: renesas: r9a07g044: Add TSU clock and reset entry	Biju Das	1	-0/+3
2021-11-19	clk: renesas: r9a07g044: Add RSPI clock and reset entries	Lad Prabhakar	1	-0/+9
2021-11-19	clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV	Biju Das	1	-1/+10
2021-11-15	clk: renesas: r9a07g044: Add OSTM clock and reset entries	Biju Das	1	-0/+9
2021-11-15	clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros	Biju Das	1	-6/+6
2021-11-15	clk: renesas: r9a07g044: Add WDT clock and reset entries	Biju Das	1	-0/+15
2021-11-15	clk: renesas: r9a07g044: Add clock and reset entry for SCI1	Lad Prabhakar	1	-0/+3
2021-10-08	clk: renesas: r9a07g044: Add SDHI clock and reset entries	Biju Das	1	-0/+36
2021-10-08	clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...	Lad Prabhakar	1	-0/+18
2021-09-24	clk: renesas: r9a07g044: Add GbEthernet clock/reset	Biju Das	1	-0/+10
2021-09-24	clk: renesas: r9a07g044: Add ethernet clock sources	Biju Das	1	-1/+18
2021-09-24	clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical	Biju Das	1	-0/+2
2021-07-26	clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2	Lad Prabhakar	1	-1/+2
2021-07-19	clk: renesas: r9a07g044: Add clock and reset entries for ADC	Lad Prabhakar	1	-0/+6
2021-07-19	clk: renesas: r9a07g044: Add clock and reset entries for CANFD	Lad Prabhakar	1	-0/+4
2021-07-19	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	Geert Uytterhoeven	1	-1/+1
2021-07-19	clk: renesas: r9a07g044: Add GPIO clock and reset entries	Lad Prabhakar	1	-0/+5
2021-07-19	clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries	Biju Das	1	-0/+20
2021-07-19	clk: renesas: r9a07g044: Add USB clocks/resets	Biju Das	1	-0/+12
2021-07-19	clk: renesas: r9a07g044: Add DMAC clocks/resets	Biju Das	1	-0/+8
2021-07-19	clk: renesas: r9a07g044: Add I2C clocks/resets	Biju Das	1	-0/+12
2021-07-12	dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions	Biju Das	1	-26/+36
2021-07-12	clk: renesas: r9a07g044: Add P2 Clock support	Biju Das	1	-0/+4
2021-07-12	clk: renesas: r9a07g044: Fix P1 Clock	Biju Das	1	-3/+3
2021-07-12	clk: renesas: r9a07g044: Rename divider table	Biju Das	1	-3/+4
2021-06-10	clk: renesas: Add support for R9A07G044 SoC	Lad Prabhakar	1	-0/+127