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path: root/drivers/clk/tegra
AgeCommit message (Expand)AuthorFilesLines
2018-10-16clk: tegra210: Include size.h for compilation easeGravatar Stephen Boyd 1-0/+1
2018-10-16clk: tegra: Fixes for MBIST work aroundGravatar Joseph Lo 1-3/+3
2018-10-16clk: tegra: probe deferral error reportingGravatar Marcel Ziswiler 1-2/+6
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Gravatar Stephen Boyd 8-40/+343
2018-08-14Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Gravatar Stephen Boyd 4-7/+15
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksGravatar Peter De-Schrijver 3-15/+12
2018-07-25clk: tegra: Add sdmmc mux divider clockGravatar Peter De-Schrijver 3-0/+278
2018-07-25clk: tegra: Refactor fractional divider calculationGravatar Peter De Schrijver 4-25/+52
2018-07-25clk: tegra: Fix includes required by fence_udelay()Gravatar Aapo Vienamo 1-0/+1
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugGravatar Dmitry Osipenko 1-1/+1
2018-07-08clk: tegra: Mark Memory Controller clock as criticalGravatar Dmitry Osipenko 1-2/+3
2018-07-08clk: tegra: Make vde a child of pll_c3Gravatar Thierry Reding 1-1/+1
2018-07-08clk: tegra: Make vic03 a child of pll_c3Gravatar Thierry Reding 1-0/+1
2018-07-08clk: tegra: bpmp: Don't crash when a clock fails to registerGravatar Mikko Perttunen 1-3/+9
2018-06-12treewide: kzalloc() -> kcalloc()Gravatar Kees Cook 1-3/+4
2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...Gravatar Stephen Boyd 1-31/+11
2018-06-01clk: tegra: no need to check return value of debugfs_create functionsGravatar Greg Kroah-Hartman 1-31/+11
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Gravatar Dmitry Osipenko 7-8/+39
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksGravatar Dmitry Osipenko 1-4/+2
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersGravatar Dmitry Osipenko 1-0/+14
2018-03-12clk: tegra: Fix pll_u rate configurationGravatar Marcel Ziswiler 1-0/+2
2018-03-12clk: tegra: Specify VDE clock rateGravatar Dmitry Osipenko 4-1/+4
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupGravatar Dmitry Osipenko 1-3/+3
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalGravatar Dmitry Osipenko 8-36/+26
2018-03-08clk: tegra: MBIST work around for Tegra210Gravatar Peter De Schrijver 1-2/+342
2018-03-08clk: tegra: add fence_delay for clock registersGravatar Peter De Schrijver 1-0/+7
2018-03-08clk: tegra: Add la clock for Tegra210Gravatar Peter De Schrijver 1-0/+14
2017-11-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Gravatar Linus Torvalds 13-66/+102
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGravatar Greg Kroah-Hartman 2-0/+2
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Gravatar Nicolin Chen 1-2/+2
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueGravatar Nicolin Chen 3-13/+11
2017-11-01clk: tegra: Fix cclk_lp divisor registerGravatar Michał Mirosław 1-1/+1
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzGravatar Dmitry Osipenko 1-1/+1
2017-11-01clk: tegra: Use common definition of APBDMA clock gateGravatar Dmitry Osipenko 1-5/+1
2017-11-01clk: tegra: Correct parent of the APBDMA clockGravatar Dmitry Osipenko 1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryGravatar Dmitry Osipenko 4-0/+4
2017-11-01clk: tegra: Mark APB clock as criticalGravatar Jon Hunter 1-1/+1
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initGravatar Bhumika Goyal 1-8/+8
2017-10-19clk: tegra: Fix sor1_out clock implementationGravatar Thierry Reding 2-16/+47
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Gravatar Thierry Reding 4-13/+4
2017-10-19clk: tegra: Add peripheral clock registration helperGravatar Thierry Reding 2-0/+11
2017-10-19clk: tegra: Check BPMP response return codeGravatar Timo Alho 1-5/+10
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationGravatar Alex Frid 1-2/+4
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayGravatar Alex Frid 1-3/+3
2017-08-23clk: tegra: Fix T210 PLLRE registrationGravatar Alex Frid 1-20/+1
2017-08-23clk: tegra: Update T210 PLLSS (D2/DP) registrationGravatar Alex Frid 1-39/+9
2017-08-23clk: tegra: Re-factor T210 PLLX registrationGravatar Alex Frid 4-49/+10
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyGravatar Peter De Schrijver 1-2/+4
2017-08-23clk: tegra: change post IDDQ release delay to 5usGravatar Peter De Schrijver 1-1/+1
2017-08-23clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CGravatar Alex Frid 1-1/+2