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path: root/drivers/clk/zte
AgeCommit message (Expand)AuthorFilesLines
2019-08-16clk: zx296718: Don't reference clk_init_data after registrationGravatar Stephen Boyd 1-60/+49
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Gravatar Thomas Gleixner 4-16/+4
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigGravatar Thomas Gleixner 1-0/+1
2017-12-21clk: move clock common macros out from vendor directoriesGravatar Chunyan Zhang 1-18/+0
2017-08-30clk: zte: constify clk_div_tableGravatar Arvind Yadav 1-3/+3
2017-06-19clk: zx296718: export I2S mux clocksGravatar Shawn Guo 1-4/+4
2017-04-12clk: zte: Mark pll config tables as constGravatar Stephen Boyd 1-2/+2
2017-04-12clk: zte: add pll_vga clock for zx296718Gravatar Shawn Guo 1-0/+24
2017-04-12clk: zte: pd_bit is not 0 on zx296718Gravatar Shawn Guo 2-2/+16
2017-04-12clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksGravatar Shawn Guo 1-3/+3
2017-02-10clk: zte: add i2s clocks for zx296718Gravatar Baoyou Xie 1-0/+4
2017-01-09clk: zte: add audio clocks for zx296718Gravatar Jun Nie 3-0/+275
2017-01-09clk: zx296718: do not panic on failureGravatar Shawn Guo 1-9/+18
2016-09-23clk: zx296718: register driver earlier with core_initcallGravatar Shawn Guo 1-1/+5
2016-09-16clk: zx: fix pointer case warningsGravatar Arnd Bergmann 1-10/+10
2016-09-16clk: zx296718: use builtin_platform_driver to simplify the codeGravatar Wei Yongjun 1-5/+1
2016-09-14clk: zx: register ZX296718 clocksGravatar Jun Nie 3-0/+1050
2016-09-14clk: zx: reform pll config info to ease code extensionGravatar Jun Nie 2-9/+16
2016-04-15clk: zte: Remove CLK_IS_ROOTGravatar Stephen Boyd 1-2/+1
2015-07-28clk: zx: Constify parent names in clock init dataGravatar Jun Nie 1-20/+20
2015-07-28clk: zx: Add audio and GPIO clock for zx296702Gravatar Jun Nie 1-2/+90
2015-07-28clk: zx: Add audio div clock method for zx296702Gravatar Jun Nie 3-3/+149
2015-06-11clk: zx: add clock support to zx296702Gravatar Jun Nie 4-0/+863