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path: root/drivers/clk
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2017-10-04clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycleGravatar Marek Szyprowski 1-0/+15
2017-09-29Merge tag 'v4.14-rockchip-clkfixes-1' of git://git.kernel.org/pub/scm/linux/k...Gravatar Stephen Boyd 1-5/+7
2017-09-29clk: Export clk_bulk_prepare()Gravatar Bjorn Andersson 1-0/+1
2017-09-17clk: rockchip: add sclk_timer5 as critical clock on rk3128Gravatar Elaine Zhang 1-0/+1
2017-09-17clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs errorGravatar Elaine Zhang 1-4/+4
2017-09-17clk: rockchip: add pclk_pmu as critical clock on rk3128Gravatar Elaine Zhang 1-1/+2
2017-09-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Gravatar Linus Torvalds 114-1037/+8040
2017-09-10Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/gi...Gravatar Linus Torvalds 4-210/+21
2017-09-01clk: si5351: fix PLL resetGravatar Russell King 1-7/+5
2017-09-01clk: at91: clk-generated: make gclk determine audio_pll rateGravatar Quentin Schulz 1-6/+57
2017-09-01clk: at91: clk-generated: create function to find best_diffGravatar Quentin Schulz 1-14/+27
2017-09-01clk: at91: add audio pll clock driversGravatar Quentin Schulz 2-0/+537
2017-09-01clk: at91: clk-generated: remove useless divisor loopGravatar Quentin Schulz 1-13/+12
2017-09-01clk: mb86s7x: Drop non-building driverGravatar Andreas Färber 2-391/+0
2017-08-31clk: ti: check for null return in strrchr to avoid null dereferencingGravatar Colin Ian King 1-1/+1
2017-08-31clk: Don't write error code into divider registerGravatar Alex Frid 1-2/+4
2017-08-31clk: uniphier: add video input subsystem clockGravatar Katsuhiro Suzuki 1-0/+6
2017-08-31clk: uniphier: add audio system clockGravatar Katsuhiro Suzuki 1-0/+12
2017-08-31clk: stm32h7: Add stm32h743 clock driverGravatar Gabriel Fernandez 2-0/+1411
2017-08-31clk: gate: expose clk_gate_ops::is_enabledGravatar Gabriel Fernandez 1-1/+2
2017-08-31clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()Gravatar Gabriel Fernandez 1-6/+6
2017-08-31clk: uniphier: add PXs3 clock dataGravatar Masahiro Yamada 3-0/+43
2017-08-31clk: hi6220: change watchdog clock sourceGravatar Leo Yan 1-3/+3
2017-08-31clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808Gravatar Elaine Zhang 1-2/+2
2017-08-31clk: cs2000: Add cs2000_set_saved_rateGravatar Gaku Inami 1-4/+10
2017-08-31clk: imx51: propagate rate across ipu_di*_selGravatar Lucas Stach 1-4/+4
2017-08-31Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern...Gravatar Stephen Boyd 4-0/+1531
2017-08-30clk: sunxi: fix uninitialized accessGravatar Arnd Bergmann 1-0/+4
2017-08-30clk: versatile: make clk_ops constGravatar Bhumika Goyal 1-1/+1
2017-08-30ARC: clk: introduce HSDK pll driverGravatar Eugeniy Paltsev 3-0/+439
2017-08-30clk: zte: constify clk_div_tableGravatar Arvind Yadav 1-3/+3
2017-08-30clk: imx: constify clk_div_tableGravatar Arvind Yadav 5-12/+12
2017-08-30clk: uniphier: add ethernet clock control supportGravatar Kunihiko Hayashi 1-0/+10
2017-08-30clk: gemini: hands off PCI OE bitGravatar Linus Walleij 1-7/+0
2017-08-30clk: ux500: prcc: constify clk_ops.Gravatar Arvind Yadav 1-3/+3
2017-08-30clk: ux500: sysctrl: constify clk_ops.Gravatar Arvind Yadav 1-4/+4
2017-08-30clk: ux500: prcmu: constify clk_ops.Gravatar Arvind Yadav 1-7/+7
2017-08-30clk: sunxi-ng: Provide a default reset hookGravatar Maxime Ripard 1-0/+12
2017-08-30clk: sunxi-ng: a83t: Support new timing mode for mmc2 clockGravatar Chen-Yu Tsai 1-8/+2
2017-08-30clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switchingGravatar Chen-Yu Tsai 2-0/+110
2017-08-30clk: sunxi-ng: Add interface to query or configure MMC timing modes.Gravatar Chen-Yu Tsai 3-0/+75
2017-08-24clk: sunxi-ng: Add sun4i/sun7i CCU driverGravatar Priit Laes 4-0/+1531
2017-08-23clk: msm8996-gcc: add missing smmu clksGravatar Srinivas Kandagatla 1-0/+28
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationGravatar Alex Frid 1-2/+4
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayGravatar Alex Frid 1-3/+3
2017-08-23clk: tegra: Fix T210 PLLRE registrationGravatar Alex Frid 1-20/+1
2017-08-23clk: tegra: Update T210 PLLSS (D2/DP) registrationGravatar Alex Frid 1-39/+9
2017-08-23clk: tegra: Re-factor T210 PLLX registrationGravatar Alex Frid 4-49/+10
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyGravatar Peter De Schrijver 1-2/+4
2017-08-23clk: tegra: change post IDDQ release delay to 5usGravatar Peter De Schrijver 1-1/+1