linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author	Files	Lines
2021-07-08	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	6	-54/+101
2021-07-02	Merge branch 'akpm' (patches from Andrew)	Linus Torvalds	1	-0/+4
2021-07-01	Revert "clk: divider: Switch from .round_rate to .determine_rate by default"	Stephen Boyd	1	-9/+9
2021-07-01	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	95	-1191/+16314
2021-07-01	kernel.h: split out panic and oops helpers	Andy Shevchenko	1	-0/+4
2021-06-30	clk: hisilicon: hi3559a: Drop __init markings everywhere	Stephen Boyd	1	-20/+19
2021-06-30	clk: meson: regmap: switch to determine_rate for the dividers	Martin Blumenstingl	1	-10/+9
2021-06-30	clk: divider: Switch from .round_rate to .determine_rate by default	Martin Blumenstingl	1	-9/+9
2021-06-30	clk: divider: Add re-usable determine_rate implementations	Martin Blumenstingl	1	-14/+61
2021-06-30	clk: k210: Fix k210_clk_set_parent()	Damien Le Moal	1	-0/+1
2021-06-30	clk: lmk04832: Fix spelling mistakes in dev_err messages and comments	Colin Ian King	1	-4/+4
2021-06-30	clk: lmk04832: fix return value check in lmk04832_probe()	Wang Hai	1	-6/+6
2021-06-30	clk: stm32mp1: fix missing spin_lock_init()	Wang Hai	1	-0/+1
2021-06-29	Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-next	Stephen Boyd	9	-73/+1710
2021-06-29	Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-...	Stephen Boyd	15	-186/+2625
2021-06-29	Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk...	Stephen Boyd	18	-113/+449
2021-06-29	Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'cl...	Stephen Boyd	23	-296/+931
2021-06-29	Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and '...	Stephen Boyd	19	-92/+1414
2021-06-28	clk: zynqmp: Handle divider specific read only flag	Rajan Vaja	1	-1/+9
2021-06-28	clk: zynqmp: Use firmware specific mux clock flags	Rajan Vaja	2	-1/+30
2021-06-28	clk: zynqmp: Use firmware specific divider clock flags	Rajan Vaja	2	-1/+33
2021-06-28	clk: zynqmp: Use firmware specific common clock flags	Rajan Vaja	6	-6/+52
2021-06-28	clk: lmk04832: Use of match table	Stephen Boyd	1	-2/+4
2021-06-28	clk: lmk04832: Depend on SPI	Stephen Boyd	1	-0/+1
2021-06-28	clk: stm32mp1: new compatible for secure RCC support	Gabriel Fernandez	2	-1/+110
2021-06-27	clk: hisilicon: Add clock driver for hi3559A SoC	Dongjiu Geng	5	-2/+856
2021-06-27	clk: si5341: Add sysfs properties to allow checking/resetting device faults	Robert Hancock	1	-0/+96
2021-06-27	clk: si5341: Add silabs,iovdd-33 property	Robert Hancock	1	-1/+9
2021-06-27	clk: si5341: Add silabs,xaxb-ext-clk property	Robert Hancock	1	-2/+7
2021-06-27	clk: si5341: Allow different output VDD_SEL values	Robert Hancock	1	-26/+110
2021-06-27	clk: si5341: Update initialization magic	Robert Hancock	1	-1/+3
2021-06-27	clk: si5341: Check for input clock presence and PLL lock on startup	Robert Hancock	1	-0/+26
2021-06-27	clk: si5341: Avoid divide errors due to bogus register contents	Robert Hancock	1	-2/+13
2021-06-27	clk: si5341: Wait for DEVICE_READY on startup	Robert Hancock	1	-0/+32
2021-06-27	drivers: ti: remove redundant error message in adpll.c	Yu Jiahua	1	-4/+1
2021-06-27	clk: st: clkgen-fsyn: embed soc clock outputs within compatible data	Alain Volmat	1	-12/+101
2021-06-27	clk: st: clkgen-pll: embed soc clock outputs within compatible data	Alain Volmat	1	-14/+106
2021-06-27	clk: st: flexgen: embed soc clock outputs within compatible data	Alain Volmat	1	-14/+353
2021-06-27	clk: st: clkgen-pll: remove unused variable of struct clkgen_pll	Alain Volmat	1	-1/+0
2021-06-27	clk: ingenic: Add support for the JZ4760	Paul Cercueil	4	-0/+441
2021-06-27	clk: ingenic: Support overriding PLLs M/N/OD calc algorithm	Paul Cercueil	2	-13/+30
2021-06-27	clk: ingenic: Remove pll_info.no_bypass_bit	Paul Cercueil	3	-8/+6
2021-06-27	clk: ingenic: Read bypass register only when there is one	Paul Cercueil	1	-8/+11
2021-06-27	clk: Support bypassing dividers	Paul Cercueil	5	-29/+42
2021-06-27	clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare	Jonathan Marek	1	-1/+1
2021-06-27	clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC	Cristian Ciocaltea	1	-1/+16
2021-06-27	clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC	Cristian Ciocaltea	1	-8/+11
2021-06-27	clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC	Cristian Ciocaltea	1	-15/+29
2021-06-27	clk: actions: Fix SD clocks factor table on Owl S500 SoC	Cristian Ciocaltea	1	-4/+2
2021-06-27	clk: actions: Fix UART clock dividers on Owl S500 SoC	Cristian Ciocaltea	1	-6/+6