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path: root/drivers/clocksource/timer-riscv.c
AgeCommit message (Expand)AuthorFilesLines
2023-02-13clocksource/drivers/riscv: Patch riscv_clock_next_event() jump before first useGravatar Matt Evans 1-5/+5
2023-02-13clocksource/drivers/riscv: Get rid of clocksource_arch_init() callbackGravatar Lad Prabhakar 1-0/+5
2023-02-13clocksource/drivers/riscv: Increase the clock source ratingGravatar Samuel Holland 1-1/+1
2023-02-13clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DTGravatar Anup Patel 1-0/+10
2022-12-01Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend"Gravatar Conor Dooley 1-1/+1
2022-08-11RISC-V: Add Sstc extension supportGravatar Palmer Dabbelt 1-1/+24
2022-08-11RISC-V: Prefer sstc extension if availableGravatar Atish Patra 1-1/+24
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Gravatar Sunil V L 1-7/+8
2022-05-18clocksource/drivers/riscv: Events are stopped during CPU suspendGravatar Samuel Holland 1-1/+1
2021-10-04RISC-V: KVM: Add timer functionalityGravatar Atish Patra 1-0/+9
2020-08-20RISC-V: Remove CLINT related code from timer and archGravatar Anup Patel 1-15/+2
2020-06-09clocksource/drivers/timer-riscv: Use per-CPU timer interruptGravatar Anup Patel 1-3/+40
2020-01-04clocksource: riscv: add notrace to riscv_sched_clockGravatar Zong Li 1-1/+1
2019-11-13riscv: add support for MMIO access to the timer registersGravatar Christoph Hellwig 1-4/+19
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeGravatar Christoph Hellwig 1-4/+4
2019-09-05riscv: don't use the rdtime(h) pseudo-instructionsGravatar Christoph Hellwig 1-13/+4
2019-08-06RISC-V: Remove per cpu clocksourceGravatar Atish Patra 1-4/+2
2019-03-23clocksource/drivers/riscv: Fix clocksource maskGravatar Atish Patra 1-3/+2
2019-02-23clocksource/drivers/riscv: Add required checks during clock source initGravatar Atish Patra 1-3/+20
2018-12-18clocksource/drivers/riscv: Change name riscv_timer to timer-riscvGravatar Daniel Lezcano 1-0/+118