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2024-04-02counter: ti-ecap-capture: Utilize COUNTER_COMP_FREQUENCY macroGravatar William Breathitt Gray 1-1/+1
Reduce boilerplate by leveraging the COUNTER_COMP_FREQUENCY() macro to define the "frequency" extension. Link: https://lore.kernel.org/r/ZfxhEKdSi1amfcJC@ishi Signed-off-by: William Breathitt Gray <wbg@kernel.org>
2024-04-02counter: ti-eqep: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: David Lechner <david@lechnology.com> Link: https://lore.kernel.org/r/bf78595f6a49be0b6bb403b466c13177d72c02b7.1710057753.git.u.kleine-koenig@pengutronix.de Signed-off-by: William Breathitt Gray <wbg@kernel.org>
2024-04-02counter: ti-ecap-capture: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/f70902b2aabecaa9295c28629cd7a8a0e6eb06d0.1710057753.git.u.kleine-koenig@pengutronix.de Signed-off-by: William Breathitt Gray <wbg@kernel.org>
2024-04-02counter: stm32-timer-cnt: add support for capture eventsGravatar Fabrice Gasnier 1-3/+131
Add support for capture events. Captured counter value for each channel can be retrieved through CCRx register. STM32 timers can have up to 4 capture channels (on input channel 1 to channel 4), hence need to check the number of channels before reading the capture data. The capture configuration is hard-coded to capture signals on both edges (non-inverted). Interrupts are used to report events independently for each channel. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Acked-by: Lee Jones <lee@kernel.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-11-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: add support for overflow eventsGravatar Fabrice Gasnier 1-1/+137
Add support overflow events. Also add the related validation and configuration routine. Register and enable interrupts to push events. STM32 Timers can have either 1 global interrupt, or 4 dedicated interrupt lines. Request only the necessary interrupt, e.g. either global interrupt that can report all event types, or update interrupt only for overflow event. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-10-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: probe number of channels from registersGravatar Fabrice Gasnier 1-0/+17
Probe the number of capture compare channels, by writing CCER register bits and read them back. Take care to restore the register original value. This is a precursor patch to support capture channels. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-9-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: introduce channelsGravatar Fabrice Gasnier 1-0/+20
Simply add channels 3 and 4 that can be used for capture. Statically add them, despite some timers doesn't have them. Rather rely on stm32_action_read that will report "none" action for these currently. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-8-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: add checks on quadrature encoder capabilityGravatar Fabrice Gasnier 1-0/+55
This is a precursor patch to support capture channels on all possible channels and stm32 timer types. Original driver was intended to be used only as quadrature encoder and simple counter on internal clock. So, add a check on encoder capability, so the driver may be probed for timer instances without encoder feature. This way, all timers may be used as simple counter on internal clock, starting from here. Encoder capability is retrieved by using the timer index (originally in stm32-timer-trigger driver and dt-bindings). The need to keep backward compatibility with existing device tree lead to parse aside trigger node. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-7-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: add counter prescaler extensionGravatar Fabrice Gasnier 1-0/+29
There's a prescaler in between the selected input signal used for counting (CK_PSC), and the counter input (CK_CNT). So add the "prescaler" extension to the counter. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-6-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: introduce clock signalGravatar Fabrice Gasnier 1-4/+49
Introduce the internal clock signal, used to count when in simple rising function. Also add the "frequency" extension to the clock signal. With this patch, signal action reports a consistent state when "increase" function is used, and the counting frequency: $ echo increase > function $ grep -H "" signal*_action signal0_action:none signal1_action:none signal2_action:rising edge $ echo 1 > enable $ cat count 25425 $ cat count 44439 $ cat ../signal2/frequency 208877930 Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-5-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: adopt signal definitionsGravatar Fabrice Gasnier 1-6/+9
Adopt signals definitions to ease later signals additions. There are no intended functional changes here. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-4-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: rename counterGravatar Fabrice Gasnier 1-1/+1
The STM32 timer may count on various sources or channels. The counter isn't specifically counting on channe1 1. So rename it to avoid a confusion. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-3-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: stm32-timer-cnt: rename quadrature signalGravatar Fabrice Gasnier 1-2/+2
Drop the Quadrature convention in the signal name. On stm32-timer: - Quadrature A signal corresponds to timer input ch1, hence "Channel 1" - Quadrature B signal corresponds to timer input ch2, hence "Channel 2". So name these signals after their channel. I suspect it referred to the (unique) quadrature counter support earlier, but the physical input really is CH1/CH2. This will be easier to support other counter modes. Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20240307133306.383045-2-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: constify the struct device_type usageGravatar Ricardo B. Marliere 1-1/+1
Since commit aed65af1cc2f ("drivers: make device_type const"), the driver core can properly handle constant struct device_type. Move the counter_device_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: "Ricardo B. Marliere" <ricardo@marliere.net> Link: https://lore.kernel.org/r/20240219-device_cleanup-counter-v1-1-24d0316ae815@marliere.net Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-04-02counter: make counter_bus_type constGravatar Ricardo B. Marliere 1-1/+1
Now that the driver core can properly handle constant struct bus_type, move the counter_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Suggested-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: "Ricardo B. Marliere" <ricardo@marliere.net> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20240204-bus_cleanup-counter-v1-1-cef9dd719bdc@marliere.net Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2024-02-16counter: fix privdata alignmentGravatar Nuno Sa 1-3/+4
Aligning to the L1 cache does not guarantee the same alignment as kmallocing an object [1]. Furthermore, in some platforms, that alignment is not sufficient for DMA safety (in case someone wants to have a DMA safe buffer in privdata) [2]. Sometime ago, we had the same fixes in IIO. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/base/devres.c#n35 [2]: https://lore.kernel.org/linux-iio/20220508175712.647246-2-jic23@kernel.org/ Fixes: c18e2760308e ("counter: Provide alternative counter registration functions") Signed-off-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20240209-counter-align-fix-v2-1-5777ea0a2722@analog.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-10-02Merge tag 'counter-fixes-for-6.6a' of ↵Gravatar Greg Kroah-Hartman 2-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-linus William writes: First set of Counter fixes for 6.6 The counter_get_ext() function would incorrectly refer to the first element of the extensions array to handle component array extensions when they are located at a different index; a fix is provided to index to the correct element in the array for this case. A fix for the microchip-tcb-capture is provided as well to correct an inverted internal GCLK logic for clock selection. * tag 'counter-fixes-for-6.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: microchip-tcb-capture: Fix the use of internal GCLK logic counter: chrdev: fix getting array extensions
2023-09-05counter: microchip-tcb-capture: Fix the use of internal GCLK logicGravatar Dharma Balasubiramani 1-1/+1
As per the datasheet, the clock selection Bits 2:0 – TCCLKS[2:0] should be set to 0 while using the internal GCLK (TIMER_CLOCK1). Fixes: 106b104137fd ("counter: Add microchip TCB capture counter") Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20230905100835.315024-1-dharma.b@microchip.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-09-04Merge tag 'mfd-next-6.6' of ↵Gravatar Linus Torvalds 1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull NFD updates from Lee Jones: "New Drivers: - Add support for the Cirrus Logic CS42L43 Audio CODEC Fix-ups: - Make use of specific printk() format tags for various optimisations - Kconfig / module modifications / tweaking - Simplify obtaining resources (memory, device data) using unified API helpers - Bunch of Device Tree additions, conversions and adaptions - Convert a bunch of Regmap configurations to use the Maple Tree cache - Ensure correct includes are present and remove some that are not required - Remove superfluous code - Reduce amount of cycles spent in critical sections - Omit the use of redundant casts and if relevant replace with better ones - Swap out raw_spin_{un}lock_irq{save,restore}() for spin_{un}lock_irq{save,restore}() Bug Fixes: - Repair theoretical deadlock situation - Fix some link-time dependencies - Use more appropriate datatype when casting" * tag 'mfd-next-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (70 commits) mfd: mc13xxx: Simplify device data fetching in probe() mfd: rz-mtu3: Replace raw_spin_lock->spin_lock() mfd: rz-mtu3: Reduce critical sections mfd: mxs-lradc: Fix Wvoid-pointer-to-enum-cast warning mfd: wm31x: Fix Wvoid-pointer-to-enum-cast warning mfd: wm8994: Fix Wvoid-pointer-to-enum-cast warning mfd: tc3589: Fix Wvoid-pointer-to-enum-cast warning mfd: lp87565: Fix Wvoid-pointer-to-enum-cast warning mfd: hi6421-pmic: Fix Wvoid-pointer-to-enum-cast warning mfd: max77541: Fix Wvoid-pointer-to-enum-cast warning mfd: max14577: Fix Wvoid-pointer-to-enum-cast warning mfd: stmpe: Fix Wvoid-pointer-to-enum-cast warning mfd: rn5t618: Remove redundant of_match_ptr() mfd: lochnagar-i2c: Remove redundant of_match_ptr() mfd: stpmic1: Remove redundant of_match_ptr() mfd: act8945a: Remove redundant of_match_ptr() mfd: rsmu_spi: Remove redundant of_match_ptr() mfd: altera-a10sr: Remove redundant of_match_ptr() mfd: rsmu_i2c: Remove redundant of_match_ptr() mfd: tc3589x: Remove redundant of_match_ptr() ...
2023-09-04counter: chrdev: fix getting array extensionsGravatar Fabrice Gasnier 1-2/+2
When trying to watch a component array extension, and the array isn't the first extended element, it fails as the type comparison is always done on the 1st element. Fix it by indexing the 'ext' array. Example on a dummy struct counter_comp: static struct counter_comp dummy[] = { COUNTER_COMP_DIRECTION(..), ..., COUNTER_COMP_ARRAY_CAPTURE(...), }; static struct counter_count dummy_cnt = { ... .ext = dummy, .num_ext = ARRAY_SIZE(dummy), } Currently, counter_get_ext() returns -EINVAL when trying to add a watch event on one of the capture array element in such example. Fixes: d2011be1e22f ("counter: Introduce the COUNTER_COMP_ARRAY component type") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20230829134029.2402868-2-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-08-18mfd: rz-mtu3: Link time dependenciesGravatar Arnd Bergmann 1-1/+1
The new set of drivers for RZ/G2L MTU3a tries to enable compile-testing the individual client drivers even when the MFD portion is disabled but gets it wrong, causing a link failure when the core is in a loadable module but the other drivers are built-in: x86_64-linux-ld: drivers/pwm/pwm-rz-mtu3.o: in function `rz_mtu3_pwm_apply': pwm-rz-mtu3.c:(.text+0x4bf): undefined reference to `rz_mtu3_8bit_ch_write' x86_64-linux-ld: pwm-rz-mtu3.c:(.text+0x509): undefined reference to `rz_mtu3_disable' arm-linux-gnueabi-ld: drivers/counter/rz-mtu3-cnt.o: in function `rz_mtu3_cascade_counts_enable_get': rz-mtu3-cnt.c:(.text+0xbec): undefined reference to `rz_mtu3_shared_reg_read' It seems better not to add the extra complexity here but instead just use a normal hard dependency, so remove the #else portion in the header along with the "|| COMPILE_TEST". This could also be fixed by having slightly more elaborate Kconfig dependencies or using the cursed 'IS_REACHABLE()' helper, but in practice it's already possible to compile-test all these drivers by enabling the mtd portion. Fixes: 254d3a727421c ("pwm: Add Renesas RZ/G2L MTU3a PWM driver") Fixes: 0be8907359df4 ("counter: Add Renesas RZ/G2L MTU3a counter driver") Fixes: 654c293e1687b ("mfd: Add Renesas RZ/G2L MTU3a core driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230719090430.1925182-1-arnd@kernel.org Signed-off-by: Lee Jones <lee@kernel.org>
2023-08-16counter: rz-mtu3-cnt: Reorder locking sequence for consistencyGravatar Biju Das 1-2/+2
All functions except rz_mtu3_count_enable_write(), call pm_runtime_{get,put} inside the lock. For consistency do the same here. Reported-by: Pavel Machek <pavel@denx.de> Closes: https://lore.kernel.org/r/ZH8Fmom8vZ4DwxqA@duo.ucw.cz Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230725154611.227556-1-biju.das.jz@bp.renesas.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-08-16counter: Explicitly include correct DT includesGravatar Rob Herring 1-1/+0
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714174357.4053541-1-robh@kernel.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-08-04Merge tag 'counter-fixes-for-6.5a' of ↵Gravatar Greg Kroah-Hartman 1-7/+7
git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-linus William writes: First set of Counter fixes for 6.5 In commit d428487471ba ("counter: i8254: Introduce the Intel 8254 interface library module"), the misplacement of the I8254 Kconfig entry results in the "Counter support" submenu items disappearing in menuconfig. A fix is provided to reposition the I8254 Kconfig entry to restore the intended submenu behavior. * tag 'counter-fixes-for-6.5a' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: Fix menuconfig "Counter support" submenu entries disappearance
2023-06-21counter: Fix menuconfig "Counter support" submenu entries disappearanceGravatar William Breathitt Gray 1-7/+7
The current placement of the I8254 Kconfig entry results in the disappearance of the "Counter support" submenu items in menuconfig. Move the I8254 above the menuconfig COUNTER entry to restore the intended submenu behavior. Fixes: d428487471ba ("counter: i8254: Introduce the Intel 8254 interface library module") Reported-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Closes: https://lore.kernel.org/all/32ddaa7b-53a8-d61f-d526-b545bd561337@linux.intel.com/ Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20230620170159.556788-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-06-15Merge tag 'counter-updates-for-6.5a' of ↵Gravatar Greg Kroah-Hartman 6-367/+916
git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-next William writes: First set of Counter updates for the 6.5 cycle Biggest changes in this set include the introduction of a new Intel 8254 interface library module and the refactoring of the existing 104-quad-8 modules to migrate it to the regmap API. Some other minor cleanups touching tools/counter and stm32-timer-cnt are also present. Changes * 104-quad-8 - Remove reference in Kconfig to 25-bit counter value - Utilize bitfield access macros - Refactor to buffer states for CMR, IOR, and IDR - Utilize helper functions to handle PR, FLAG and PSC - Migrate to the regmap API * i8254 - Introduce the Intel 8254 interface library module * stm32-timer-cnt - Reset TIM_TISEL to its default value in probe * tools/counter - Add .gitignore - Remove lingering 'include' directories on make clean * tag 'counter-updates-for-6.5a' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: i8254: Introduce the Intel 8254 interface library module counter: 104-quad-8: Migrate to the regmap API counter: 104-quad-8: Utilize helper functions to handle PR, FLAG and PSC counter: 104-quad-8: Refactor to buffer states for CMR, IOR, and IDR counter: 104-quad-8: Utilize bitfield access macros tools/counter: Makefile: Remove lingering 'include' directories on make clean tools/counter: Add .gitignore counter: stm32-timer-cnt: Reset TIM_TISEL to its default value in probe counter: 104-quad-8: Remove reference in Kconfig to 25-bit counter value
2023-06-08counter: i8254: Introduce the Intel 8254 interface library moduleGravatar William Breathitt Gray 4-1/+470
Exposes consumer library functions providing support for interfaces compatible with the venerable Intel 8254 Programmable Interval Timer (PIT). The Intel 8254 PIT first appeared in the early 1980s and was used initially in IBM PC compatibles. The popularity of the original Intel 825x family of chips led to many subsequent variants and clones of the interface in various chips and integrated circuits. Although still popular, interfaces compatible with the Intel 8254 PIT are nowdays typically found embedded in larger VLSI processing chips and FPGA components rather than as discrete ICs. A CONFIG_I8254 Kconfig option is introduced by this patch. Modules wanting access to these i8254 library functions should select this Kconfig option, and import the I8254 symbol namespace. Link: https://lore.kernel.org/r/f6fe32c2db9525d816ab1a01f45abad56c081652.1681665189.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-31counter: add HAS_IOPORT_MAP dependencyGravatar Niklas Schnelle 1-0/+1
The 104_QUAD_8 counter driver uses devm_ioport_map() without depending on HAS_IOPORT_MAP. This means the driver is not usable on platforms such as s390 which do not support I/O port mapping. Add the missing HAS_IOPORT_MAP dependency to make this explicit. Co-developed-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Link: https://lore.kernel.org/r/20230522105049.1467313-8-schnelle@linux.ibm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-05-18counter: 104-quad-8: Migrate to the regmap APIGravatar William Breathitt Gray 2-137/+229
The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. With regmap we get boundary checks, read-write permissions, operation synchronization locks, and more for free. Most important of all, rather than rolling our own we utilize implementations that are known to work and gain from any future improvements and fixes that come. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/1f1f7920d2be94aedb6fdf49f429fe6137c8cb24.1681753140.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-18counter: 104-quad-8: Utilize helper functions to handle PR, FLAG and PSCGravatar William Breathitt Gray 1-52/+45
The Preset Register (PR), Flag Register (FLAG), and Filter Clock Prescaler (PSC) have common usage patterns. Wrap up such usage into dedicated functions to improve code clarity. Link: https://lore.kernel.org/r/a2d663337bf2907e0283023c06b1ddcbb32f7f6d.1681753140.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-18counter: 104-quad-8: Refactor to buffer states for CMR, IOR, and IDRGravatar William Breathitt Gray 1-183/+105
The 104-quad-8 driver buffers the device configuration states separately, however each device has only three control registers: CMR, IOR, and IDR. Refactoring to buffer the states of these control registers rather than each configuration separately results in succinct code that more closely matches what is happening on the device. Link: https://lore.kernel.org/r/48071415aed43ecdd8595174191b0d906205a9e3.1681753140.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-18counter: 104-quad-8: Utilize bitfield access macrosGravatar William Breathitt Gray 1-102/+172
The 104-QUAD-8 features several registers with various bitfields. Utilize bitfield access macros such as u8_get_bits() and u8_encode_bits() to make the code easier to read and the intent clearer. Suggested-by: Jonathan Cameron <jic23@kernel.org> Link: https://lore.kernel.org/r/7cea5ad049c75d8d1c6f25e288aa743a8d2a25d8.1681753140.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-09counter: stm32-timer-cnt: Reset TIM_TISEL to its default value in probeGravatar Uwe Kleine-König 1-0/+3
The driver assumes that the input selection register (TIM_TISEL) is at its reset default value. Usually this is the case, but the bootloader might have modified it. This bases on a similar patch submitted by Olivier Moysan for pwm-stm32. Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230413212339.3611722-1-u.kleine-koenig@pengutronix.de/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-09counter: 104-quad-8: Remove reference in Kconfig to 25-bit counter valueGravatar William Breathitt Gray 1-3/+3
Support for 25-bit counter values was removed in commit 4aa3b75c7460 ("counter: 104-quad-8: Fix race condition between FLAG and CNTR reads"). Adjust the Kconfig description of CONFIG_104_QUAD_8 to remove reference of 25-bit counter values. Link: https://lore.kernel.org/r/20230410134516.102886-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-05-02Merge tag 'mfd-next-6.4' of ↵Gravatar Linus Torvalds 3-0/+918
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Drivers: - Add support for Renesas RZ/G2L MTU3 New Device Support: - Add support for Lenovo Yoga Book X90F to Intel CHT WC - Add support for MAX5970 and MAX5978 to Simple MFD (I2C) - Add support for Meteor Lake PCH-S LPSS PCI to Intel LPSS PCI - Add support for AXP15060 PMIC to X-Powers PMIC collection Remove Device Support: - Remove support for Samsung 5M8751 and S5M8763 PMIC devices New Functionality: - Convert deprecated QCOM IRQ Chip to config registers - Add support for 32-bit address spaces to Renesas SMUs Fix-ups: - Make use of APIs / MACROs designed to simplify and demystify - Add / improve Device Tree bindings - Memory saving struct layout optimisations - Remove old / deprecated functionality - Factor out unassigned register addresses from ranges - Trivial: Spelling fixes, renames and coding style fixes - Rid 'defined but not used' warnings - Remove ineffective casts and pointer stubs Bug Fixes: - Fix incorrectly non-inverted mask/unmask IRQs on QCOM platforms - Remove MODULE_*() helpers from non-tristate drivers - Do not attempt to use out-of-range memory addresses associated with io_base - Provide missing export helpers - Fix remap bulk read optimisation fallout - Fix memory leak issues in error paths" * tag 'mfd-next-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (88 commits) dt-bindings: mfd: ti,j721e-system-controller: Add SoC chip ID leds: bd2606mvv: Driver for the Rohm 6 Channel i2c LED driver dt-bindings: mfd: qcom,spmi-pmic: Document flash LED controller dt-bindings: mfd: x-powers,axp152: Document the AXP15060 variant mfd: axp20x: Add support for AXP15060 PMIC dt-bindings: mfd: x-powers,axp152: Document the AXP313a variant counter: rz-mtu3-cnt: Unlock on error in rz_mtu3_count_ceiling_write() dt-bindings: mfd: dlg,da9063: Document voltage monitoring dt-bindings: mfd: stm32: Remove unnecessary blank lines dt-bindings: mfd: qcom,spmi-pmic: Use generic ADC node name in examples dt-bindings: mfd: syscon: Add nuvoton,ma35d1-sys compatible MAINTAINERS: Add entries for Renesas RZ/G2L MTU3a counter driver counter: Add Renesas RZ/G2L MTU3a counter driver Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select mfd: Add Renesas RZ/G2L MTU3a core driver dt-bindings: timer: Document RZ/G2L MTU3a bindings mfd: rsmu_i2c: Convert to i2c's .probe_new() again mfd: intel-lpss: Add Intel Meteor Lake PCH-S LPSS PCI IDs mfd: dln2: Fix memory leak in dln2_probe() mfd: axp20x: Fix axp288 writable-ranges ...
2023-04-26counter: rz-mtu3-cnt: Unlock on error in rz_mtu3_count_ceiling_write()Gravatar Dan Carpenter 1-2/+6
These error paths need to call mutex_unlock(&priv->lock) before returning. The lock is taken in rz_mtu3_lock_if_counter_is_valid(). Fixes: 25d21447d896 ("counter: Add Renesas RZ/G2L MTU3a counter driver") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Acked-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/7b535d6b-6031-493a-84f6-82842089e637@kili.mountain
2023-04-26counter: Add Renesas RZ/G2L MTU3a counter driverGravatar Biju Das 3-0/+914
Add RZ/G2L MTU3a counter driver. This IP supports the following phase counting modes on MTU1 and MTU2 channels 1) 16-bit phase counting modes on MTU1 and MTU2 channels. 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. This patch adds 3 counter value channels. count0: 16-bit phase counter value channel on MTU1 count1: 16-bit phase counter value channel on MTU2 count2: 32-bit phase counter value channel by cascading MTU1 and MTU2 channels. The external input phase clock pin for the counter value channels are as follows: count0: "MTCLKA-MTCLKB" count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" Use the sysfs variable "external_input_phase_clock_select" to select the external input phase clock pin and "cascade_counts_enable" to enable/ disable cascading of channels. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Acked-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230330111632.169434-5-biju.das.jz@bp.renesas.com
2023-03-18counter: 104-quad-8: Fix Synapse action reported for Index signalsGravatar William Breathitt Gray 1-1/+1
Signal 16 and higher represent the device's Index lines. The priv->preset_enable array holds the device configuration for these Index lines. The preset_enable configuration is active low on the device, so invert the conditional check in quad8_action_read() to properly handle the logical state of preset_enable. Fixes: f1d8a071d45b ("counter: 104-quad-8: Add Generic Counter interface support") Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20230316203426.224745-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-03-18counter: 104-quad-8: Fix race condition between FLAG and CNTR readsGravatar William Breathitt Gray 1-21/+8
The Counter (CNTR) register is 24 bits wide, but we can have an effective 25-bit count value by setting bit 24 to the XOR of the Borrow flag and Carry flag. The flags can be read from the FLAG register, but a race condition exists: the Borrow flag and Carry flag are instantaneous and could change by the time the count value is read from the CNTR register. Since the race condition could result in an incorrect 25-bit count value, remove support for 25-bit count values from this driver; hard-coded maximum count values are replaced by a LS7267_CNTR_MAX define for consistency and clarity. Fixes: 28e5d3bb0325 ("iio: 104-quad-8: Add IIO support for the ACCES 104-QUAD-8") Cc: <stable@vger.kernel.org> # 6.1.x Cc: <stable@vger.kernel.org> # 6.2.x Link: https://lore.kernel.org/r/20230312231554.134858-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-01-18counter: fix dependency references for config MICROCHIP_TCB_CAPTUREGravatar Lukas Bulwahn 1-1/+1
Commit dfeef15e73ca ("counter: microchip-tcp-capture: Add appropriate arch deps for TCP driver") intends to add appropriate dependencies for the config MICROCHIP_TCB_CAPTURE. It however prefixes the intended configs with CONFIG, but in Kconfig files in contrast to source files, the configs are referenced to without prefixing them with CONFIG. Fix the dependency references due to this minor misconception. Fixes: dfeef15e73ca ("counter: microchip-tcp-capture: Add appropriate arch deps for TCP driver") Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20230118074659.5909-1-lukas.bulwahn@gmail.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-01-13counter: microchip-tcp-capture: Add appropriate arch deps for TCP driverGravatar Peter Robinson 1-0/+1
Add the CONFIG_SOC_AT91SAM9 and CONFIG_SOC_SAM_V7 deps for the Microchip SoCs that support this IP block/driver plus compile time testing. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Link: https://lore.kernel.org/r/20230108074750.443705-4-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-01-13counter: ftm-quaddec: Depend on the Layerscape SoCGravatar Peter Robinson 1-0/+1
At the moment only the Freescale LS1021A is the only HW that supports this IP block so add an appropriate dependency and compile test. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Link: https://lore.kernel.org/r/20230108074750.443705-3-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-01-13counter: intel-qep: Depend on X86Gravatar Peter Robinson 1-0/+1
Limit the Intel counter driver to X86, it doesn't make sense to build it for all arches if the counter subsystem is enabled. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Link: https://lore.kernel.org/r/20230108074750.443705-2-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-01-13counter: Sort the Kconfig entries alphabeticallyGravatar Peter Robinson 1-44/+44
Sort the Kconfig menu alphabetically to make it easier to read as the list grows larger. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Link: https://lore.kernel.org/r/20230108074750.443705-1-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2022-11-26counter: stm32-lptimer-cnt: fix the check on arr and cmp registers updateGravatar Fabrice Gasnier 1-1/+1
The ARR (auto reload register) and CMP (compare) registers are successively written. The status bits to check the update of these registers are polled together with regmap_read_poll_timeout(). The condition to end the loop may become true, even if one of the register isn't correctly updated. So ensure both status bits are set before clearing them. Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2022-10-23counter: 104-quad-8: Fix race getting function mode and directionGravatar William Breathitt Gray 1-22/+42
The quad8_action_read() function checks the Count function mode and Count direction without first acquiring a lock. This is a race condition because the function mode could change by the time the direction is checked. Because the quad8_function_read() already acquires a lock internally, the quad8_function_read() is refactored to spin out the no-lock code to a new quad8_function_get() function. To resolve the race condition in quad8_action_read(), a lock is acquired before calling quad8_function_get() and quad8_direction_read() in order to get both function mode and direction atomically. Fixes: f1d8a071d45b ("counter: 104-quad-8: Add Generic Counter interface support") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20221020141121.15434-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2022-10-23counter: microchip-tcb-capture: Handle Signal1 read and SynapseGravatar William Breathitt Gray 1-4/+14
The signal_read(), action_read(), and action_write() callbacks have been assuming Signal0 is requested without checking. This results in requests for Signal1 returning data for Signal0. This patch fixes these oversights by properly checking for the Signal's id in the respective callbacks and handling accordingly based on the particular Signal requested. The trig_inverted member of the mchp_tc_data is removed as superfluous. Fixes: 106b104137fd ("counter: Add microchip TCB capture counter") Cc: stable@vger.kernel.org Reviewed-by: Kamel Bouhara <kamel.bouhara@bootlin.com> Link: https://lore.kernel.org/r/20221018121014.7368-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2022-10-17counter: ti-ecap-capture: fix IS_ERR() vs NULL checkGravatar Dan Carpenter 1-2/+2
The devm_counter_alloc() function returns NULL on error. It doesn't return error pointers. Fixes: 4e2f42aa00b6 ("counter: ti-ecap-capture: capture driver support for ECAP") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Julien Panis <jpanis@baylibre.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/Y0bUbZvfDJHBG9C6@kili/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2022-10-17counter: Reduce DEFINE_COUNTER_ARRAY_POLARITY() to defining counter_arrayGravatar William Breathitt Gray 1-1/+2
A spare warning was reported for drivers/counter/ti-ecap-capture.c:: sparse warnings: (new ones prefixed by >>) >> drivers/counter/ti-ecap-capture.c:380:8: sparse: sparse: symbol 'ecap_cnt_pol_array' was not declared. Should it be static? vim +/ecap_cnt_pol_array +380 drivers/counter/ti-ecap-capture.c 379 > 380 static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_avail, ECAP_NB_CEVT); 381 The first argument to the DEFINE_COUNTER_ARRAY_POLARITY() macro is a token serving as the symbol name in the definition of a new struct counter_array structure. However, this macro actually expands to two statements:: #define DEFINE_COUNTER_ARRAY_POLARITY(_name, _enums, _length) \ DEFINE_COUNTER_AVAILABLE(_name##_available, _enums); \ struct counter_array _name = { \ .type = COUNTER_COMP_SIGNAL_POLARITY, \ .avail = &(_name##_available), \ .length = (_length), \ } Because of this, the "static" on line 380 only applies to the first statement. This patch splits out the DEFINE_COUNTER_AVAILABLE() line and leaves DEFINE_COUNTER_ARRAY_POLARITY() as a simple structure definition to avoid issues like this. Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/all/202210020619.NQbyomII-lkp@intel.com/ Cc: Julien Panis <jpanis@baylibre.com> Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2022-10-08Merge tag 'gpio-updates-for-v6.1-rc1' of ↵Gravatar Linus Torvalds 1-2/+3
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "We have a single new driver, support for a bunch of new models, improvements in drivers and core gpiolib code as well device-tree bindings changes. Summary: New driver: - IMX System Controller Unit GPIOs GPIO core: - add fdinfo output for the GPIO character device file descriptors (allows user-space to determine which processes own which GPIO lines) - improvements to OF GPIO code - new quirk for Asus UM325UAZ in gpiolib-acpi - new quirk for Freescale SPI in gpiolib-of Driver improvements: - add a new macro that reduces the amount of boilerplate code in ISA drivers and use it in relevant drivers - support two new models in gpio-pca953x - support new model in gpio-f7188x - convert more drivers to use immutable irq chips - other minor tweaks Device-tree bindings: - add DT bindings for gpio-imx-scu - convert Xilinx GPIO bindings to YAML - reference the properties from the SPI peripheral device-tree bindings instead of providing custom ones in the GPIO controller document - add parsing of GPIO hog nodes to the DT bindings for gpio-mpfs-gpio - relax the node name requirements in gpio-stmpe - add new models for gpio-rcar and gpio-pxa95xx - add a new vendor prefix: Diodes (for Diodes, Inc.) Misc: - pulled in the immutable branch from the x86 platform drivers tree including support for a new simatic board that depends on GPIO changes" * tag 'gpio-updates-for-v6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (36 commits) gpio: tc3589x: Make irqchip immutable gpiolib: cdev: add fdinfo output for line request file descriptors gpio: twl4030: Reorder functions which allows to drop a forward declaraion gpiolib: fix OOB access in quirk callbacks gpiolib: of: factor out conversion from OF flags gpiolib: rework quirk handling in of_find_gpio() gpiolib: of: make Freescale SPI quirk similar to all others gpiolib: of: do not ignore requested index when applying quirks gpio: ws16c48: Ensure number of irq matches number of base gpio: 104-idio-16: Ensure number of irq matches number of base gpio: 104-idi-48: Ensure number of irq matches number of base gpio: 104-dio-48e: Ensure number of irq matches number of base counter: 104-quad-8: Ensure number of irq matches number of base isa: Introduce the module_isa_driver_with_irq helper macro gpio: pca953x: Add support for PCAL6534 gpio: pca953x: Swap if statements to save later complexity gpio: pca953x: Fix pca953x_gpio_set_pull_up_down() dt-bindings: gpio: pca95xx: add entry for pcal6534 and PI4IOE5V6534Q dt-bindings: vendor-prefixes: add Diodes gpio: mt7621: Switch to use platform_get_irq() function ...
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