linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author	Files	Lines
2024-03-12	cxl/region: Add memory hotplug notifier for cxl region	Dave Jiang	1	-0/+3
2024-03-12	cxl/region: Calculate performance data for a region	Dave Jiang	1	-0/+4
2024-03-12	cxl: Split out host bridge access coordinates	Dave Jiang	1	-0/+2
2024-03-12	cxl: Split out combine_coordinates() for common shared usage	Dave Jiang	1	-0/+4
2024-03-12	ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...	Dave Jiang	1	-1/+1
2024-02-16	cxl: Fix sysfs export of qos_class for memdev	Dave Jiang	1	-0/+2
2024-01-05	Merge branch 'for-6.7/cxl' into for-6.8/cxl	Dan Williams	1	-2/+0
2024-01-05	cxl: Convert find_cxl_root() to return a 'struct cxl_root *'	Dave Jiang	1	-7/+7
2024-01-05	cxl: Introduce put_cxl_root() helper	Dave Jiang	1	-0/+3
2024-01-04	cxl/port: Fix missing target list lock	Dan Williams	1	-2/+0
2023-12-22	cxl: Add helper function that calculate performance data for downstream ports	Dave Jiang	1	-0/+3
2023-12-22	cxl: Store the access coordinates for the generic ports	Dave Jiang	1	-0/+2
2023-12-22	cxl: Calculate and store PCI link latency for the downstream ports	Dave Jiang	1	-0/+4
2023-12-22	cxl: Add support for _DSM Function for retrieving QTG ID	Dave Jiang	1	-0/+25
2023-12-22	cxl: Add callback to parse the SSLBIS subtable from CDAT	Dave Jiang	1	-0/+4
2023-12-22	cxl: Add callback to parse the DSMAS subtables from CDAT	Dave Jiang	1	-0/+2
2023-10-31	Merge branch 'for-6.7/cxl-commited' into cxl/next	Dan Williams	1	-0/+1
2023-10-31	Merge branch 'for-6.7/cxl-qtg' into cxl/next	Dan Williams	1	-0/+3
2023-10-27	cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute	Dave Jiang	1	-0/+3
2023-10-27	cxl: Add cxl_decoders_committed() helper	Dave Jiang	1	-0/+1
2023-10-27	cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm	Robert Richter	1	-2/+1
2023-10-27	cxl/pci: Map RCH downstream AER registers for logging protocol errors	Terry Bowman	1	-0/+10
2023-10-27	cxl/pci: Add RCH downstream port AER register discovery	Robert Richter	1	-0/+7
2023-10-27	cxl/port: Remove Component Register base address from struct cxl_port	Robert Richter	1	-2/+0
2023-10-27	cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map	Robert Richter	1	-4/+4
2023-10-27	cxl/core/regs: Rename @dev to @host in struct cxl_register_map	Robert Richter	1	-2/+2
2023-06-25	Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl	Dan Williams	1	-25/+32
2023-06-25	Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl	Dan Williams	1	-0/+16
2023-06-25	Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxl	Dan Williams	1	-7/+9
2023-06-25	Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl	Dan Williams	1	-6/+5
2023-06-25	Revert "cxl/port: Enable the HDM decoder capability for switch ports"	Dan Williams	1	-1/+0
2023-06-25	cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM	Dan Williams	1	-1/+1
2023-06-25	cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}	Dan Williams	1	-2/+2
2023-06-25	cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output	Dan Williams	1	-2/+2
2023-06-25	cxl/region: Flag partially torn down regions as unusable	Dan Williams	1	-0/+8
2023-06-25	cxl/region: Move cache invalidation before region teardown, and before setup	Dan Williams	1	-7/+1
2023-06-25	cxl/port: Store the downstream port's Component Register mappings in struct c...	Robert Richter	1	-0/+2
2023-06-25	cxl/port: Store the port's Component Register mappings in struct cxl_port	Robert Richter	1	-0/+2
2023-06-25	cxl/pci: Early setup RCH dport component registers from RCRB	Robert Richter	1	-0/+2
2023-06-25	cxl/port: Remove Component Register base address from struct cxl_dport	Robert Richter	1	-2/+0
2023-06-25	cxl/pci: Refactor component register discovery for reuse	Terry Bowman	1	-0/+1
2023-06-25	cxl/core/regs: Add @dev to cxl_register_map	Robert Richter	1	-4/+6
2023-06-25	cxl: Rename 'uport' to 'uport_dev'	Dan Williams	1	-6/+7
2023-06-25	cxl: Rename member @dport of struct cxl_dport to @dport_dev	Robert Richter	1	-2/+2
2023-06-25	cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability	Dan Williams	1	-2/+7
2023-06-25	cxl/acpi: Probe RCRB later during RCH downstream port creation	Robert Richter	1	-9/+3
2023-05-30	cxl/pci: Find and register CXL PMU devices	Jonathan Cameron	1	-0/+13
2023-05-30	cxl: Add functions to get an instance of / count regblocks of a given type	Jonathan Cameron	1	-0/+3
2023-05-23	cxl/mbox: Add background cmd handling machinery	Davidlohr Bueso	1	-0/+8
2023-05-18	cxl/port: Enable the HDM decoder capability for switch ports	Dan Williams	1	-0/+1