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drivers
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cxl
Age
Commit message (
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Author
Files
Lines
2022-04-08
cxl/pci: Drop shadowed variable
Dan Williams
1
-1
/
+0
2022-03-22
cxl/core/port: Fix NULL but dereferenced coccicheck error
Wan Jiabing
1
-1
/
+4
2022-02-17
cxl/port: Hold port reference until decoder release
Dan Williams
1
-0
/
+4
2022-02-17
cxl/port: Fix endpoint refcount leak
Dan Williams
1
-1
/
+2
2022-02-11
cxl/core: Fix cxl_device_lock() class detection
Dan Williams
1
-1
/
+1
2022-02-11
cxl/core/port: Fix unregister_port() lock assertion
Dan Williams
1
-4
/
+20
2022-02-08
cxl/regs: Fix size of CXL Capability Header Register
Jonathan Cameron
1
-2
/
+2
2022-02-08
cxl/core/port: Handle invalid decoders
Dan Williams
1
-6
/
+30
2022-02-08
cxl/core/port: Fix / relax decoder target enumeration
Dan Williams
2
-2
/
+5
2022-02-08
cxl/core/port: Add endpoint decoders
Ben Widawsky
4
-16
/
+73
2022-02-08
cxl/core: Move target_list out of base decoder attributes
Dan Williams
1
-1
/
+2
2022-02-08
cxl/mem: Add the cxl_mem driver
Ben Widawsky
9
-5
/
+391
2022-02-08
cxl/core/port: Add switch port enumeration
Dan Williams
3
-25
/
+438
2022-02-08
cxl/memdev: Add numa_node attribute
Dan Williams
1
-0
/
+17
2022-02-08
cxl/pci: Emit device serial number
Dan Williams
3
-0
/
+14
2022-02-08
cxl/pci: Implement wait for media active
Ben Widawsky
2
-1
/
+50
2022-02-08
cxl/pci: Retrieve CXL DVSEC memory info
Ben Widawsky
3
-0
/
+146
2022-02-08
cxl/pci: Cache device DVSEC offset
Ben Widawsky
2
-0
/
+8
2022-02-08
cxl/pci: Store component register base in cxlds
Ben Widawsky
2
-0
/
+14
2022-02-08
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
7
-24
/
+24
2022-02-08
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
8
-29
/
+108
2022-02-08
cxl/core: Emit modalias for CXL devices
Dan Williams
1
-9
/
+17
2022-02-08
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
8
-49
/
+348
2022-02-08
cxl/core: Generalize dport enumeration in the core
Dan Williams
6
-110
/
+167
2022-02-08
cxl/pci: Rename pci.h to cxlpci.h
Dan Williams
4
-3
/
+4
2022-02-08
cxl/port: Up-level cxl_add_dport() locking requirements to the caller
Dan Williams
2
-2
/
+3
2022-02-08
cxl/pmem: Introduce a find_cxl_root() helper
Dan Williams
3
-4
/
+60
2022-02-08
cxl/port: Introduce cxl_port_to_pci_bus()
Dan Williams
3
-5
/
+49
2022-02-08
cxl/core/port: Use dedicated lock for decoder target list
Dan Williams
2
-7
/
+25
2022-02-08
cxl: Prove CXL locking
Dan Williams
5
-24
/
+130
2022-02-08
cxl/core: Track port depth
Ben Widawsky
2
-0
/
+4
2022-02-08
cxl/core/port: Make passthrough decoder init implicit
Ben Widawsky
2
-6
/
+8
2022-02-08
cxl/core: Fix cxl_probe_component_regs() error message
Dan Williams
1
-1
/
+1
2022-02-08
cxl/core/port: Clarify decoder creation
Ben Widawsky
3
-11
/
+92
2022-02-08
cxl/core: Convert decoder range to resource
Ben Widawsky
3
-18
/
+35
2022-02-08
cxl/decoder: Hide physical address information from non-root
Dan Williams
1
-1
/
+1
2022-02-08
cxl/core/port: Rename bus.c to port.c
Dan Williams
2
-1
/
+1
2022-02-08
cxl: Introduce module_cxl_driver
Ben Widawsky
1
-0
/
+3
2022-02-08
cxl/acpi: Map component registers for Root Ports
Ben Widawsky
5
-54
/
+80
2022-02-08
cxl/pci: Add new DVSEC definitions
Ben Widawsky
1
-0
/
+15
2022-02-08
cxl: Flesh out register names
Ben Widawsky
2
-16
/
+17
2022-02-08
cxl/pci: Defer mailbox status checks to command timeouts
Dan Williams
1
-101
/
+33
2022-02-08
cxl/pci: Implement Interface Ready Timeout
Ben Widawsky
1
-0
/
+35
2022-02-08
cxl: Rename CXL_MEM to CXL_PCI
Ben Widawsky
2
-12
/
+13
2022-01-04
cxl/core: Remove cxld_const_init in cxl_decoder_alloc()
Nathan Chancellor
2
-5
/
+3
2021-11-15
cxl/pmem: Fix module reload vs workqueue state
Dan Williams
3
-3
/
+42
2021-11-15
ACPI: NUMA: Add a node and memblk for each CFMWS not in SRAT
Alison Schofield
1
-1
/
+2
2021-11-15
cxl/test: Mock acpi_table_parse_cedt()
Dan Williams
1
-0
/
+2
2021-11-15
cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpers
Dan Williams
2
-147
/
+88
2021-11-15
cxl/memdev: Remove unused cxlmd field
Ira Weiny
1
-2
/
+0
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