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path: root/drivers/edac/i10nm_base.c
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2021-06-17EDAC/Intel: Do not load EDAC driver when running as a guestGravatar Luck, Tony 1-0/+3
2021-06-17EDAC/i10nm: Add support for high bandwidth memoryGravatar Qiuxu Zhuo 1-12/+120
2021-06-17EDAC/i10nm: Add detection of memory levels for ICX/SPR serversGravatar Qiuxu Zhuo 1-0/+39
2020-11-19EDAC/i10nm: Add Intel Sapphire Rapids server supportGravatar Qiuxu Zhuo 1-9/+25
2020-11-19EDAC/i10nm: Use readl() to access MMIO registersGravatar Qiuxu Zhuo 1-4/+7
2020-06-15EDAC, {skx,i10nm}: Use CPU stepping macro to pass configurationsGravatar Qiuxu Zhuo 1-7/+5
2020-06-01Merge branches 'edac-i10nm' and 'edac-misc' into edac-updates-for-5.8Gravatar Borislav Petkov 1-5/+24
2020-05-19EDAC/skx: Use the mcmtr register to retrieve close_pg/bank_xor_enableGravatar Qiuxu Zhuo 1-1/+1
2020-04-27EDAC/i10nm: Update driver to support different bus number config register off...Gravatar Qiuxu Zhuo 1-4/+14
2020-04-27EDAC, {skx,i10nm}: Make some configurations CPU model specificGravatar Qiuxu Zhuo 1-4/+13
2020-03-24EDAC: Convert to new X86 CPU match macrosGravatar Thomas Gleixner 1-4/+4
2019-11-09EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() functionGravatar Robert Richter 1-2/+1
2019-08-28x86/intel: Aggregate microserver namingGravatar Peter Zijlstra 1-2/+2
2019-06-26EDAC, skx, i10nm: Fix source ID register offsetGravatar Qiuxu Zhuo 1-1/+1
2019-06-26EDAC, i10nm: Check ECC enabling status per channelGravatar Qiuxu Zhuo 1-3/+3
2019-06-20EDAC, i10nm: Add Intel additional Ice-Lake supportGravatar Qiuxu Zhuo 1-0/+2
2019-03-23EDAC, skx, i10nm: Make skx_common.c a pure libraryGravatar Qiuxu Zhuo 1-2/+50
2019-02-02EDAC, i10nm: Add a driver for Intel 10nm server processorsGravatar Qiuxu Zhuo 1-0/+275