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path: root/drivers/fpga/zynq-fpga.c
AgeCommit message (Expand)AuthorFilesLines
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285Gravatar Thomas Gleixner 1-9/+1
2018-11-11zynq-fpga: Only route PR via PCAP when requiredGravatar Mike Looijmans 1-0/+4
2018-10-16fpga: mgr: add devm_fpga_mgr_createGravatar Alan Tull 1-3/+2
2018-05-25fpga: manager: change api, don't use drvdataGravatar Alan Tull 1-3/+11
2017-03-17fpga: zynq: Add support for encrypted bitstreamsGravatar Moritz Fischer 1-3/+25
2017-02-10fpga zynq: Use the scatterlist interfaceGravatar Jason Gunthorpe 1-39/+135
2017-02-10fpga zynq: Check the bitstream for validityGravatar Jason Gunthorpe 1-0/+21
2017-02-10fpga zynq: Check for errors after completing DMAGravatar Jason Gunthorpe 1-22/+32
2016-11-29fpga zynq: Fix incorrect ISR state on bootupGravatar Jason Gunthorpe 1-7/+10
2016-11-29fpga zynq: Remove priv->devGravatar Jason Gunthorpe 1-11/+8
2016-11-29fpga zynq: Add missing \n to messagesGravatar Jason Gunthorpe 1-11/+11
2016-11-10fpga-mgr: add fpga image information structGravatar Alan Tull 1-4/+6
2015-10-23fpga: zynq-fpga: Fix issue with drvdata being overwritten.Gravatar Moritz Fischer 1-3/+4
2015-10-23fpga: zynq-fpga: Change fw format to handle bin instead of bit.Gravatar Moritz Fischer 1-22/+2
2015-10-23fpga: zynq-fpga: Fix unbalanced clock handlingGravatar Moritz Fischer 1-2/+2
2015-10-17fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Gravatar Moritz Fischer 1-0/+533