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path: root/drivers/gpu/drm/i915/i915_reg.h
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2011-03-16Merge commit '5359533801e3dd3abca5b7d3d985b0b33fd9fe8b' into drm-core-nextGravatar Dave Airlie 1-0/+10
2011-03-10drm/i915: Revive combination mode for backlight controlGravatar Takashi Iwai 1-0/+10
2011-03-07Merge branch 'drm-intel-fixes' into drm-intel-nextGravatar Chris Wilson 1-0/+2
2011-03-06drm/i915: Do not overflow the MMADDR write FIFOGravatar Chris Wilson 1-0/+2
2011-03-01drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"Gravatar Chris Wilson 1-1/+4
2011-02-22Merge branch 'drm-intel-fixes' into drm-intel-nextGravatar Chris Wilson 1-10/+0
2011-02-22drm/i915: Add support for limited color range of broadcast outputsGravatar Chris Wilson 1-0/+1
2011-02-21drm/i915: Do not handle backlight combination mode speciallyGravatar Indan Zupancic 1-10/+0
2011-02-16Merge branch 'drm-intel-fixes' into drm-intel-nextGravatar Chris Wilson 1-1/+3
2011-02-11drm/i915: disable PCH ports if needed when disabling a CRTCGravatar Jesse Barnes 1-0/+15
2011-02-07drm/i915: cleanup per-pipe reg usageGravatar Jesse Barnes 1-201/+231
2011-02-07drm/i915: Set the transcoder port to none when disabling DP.Gravatar Eric Anholt 1-0/+1
2011-02-02drm/i915: Invalidate TLB caches on SNB BLT/BSD ringsGravatar Chris Wilson 1-1/+3
2011-01-20Merge branch 'drm-intel-fixes' into drm-intel-nextGravatar Chris Wilson 1-0/+6
2011-01-19drm/i915: Honour LVDS sync polarity from EDIDGravatar Bryan Freed 1-0/+4
2011-01-19drm/i915: tune Sandy Bridge DRPS constantsGravatar Jesse Barnes 1-2/+15
2011-01-19drm/i915: set phase sync pointer override enable before setting phase sync po...Gravatar Jesse Barnes 1-1/+2
2011-01-19drm/i915: add PCH DPLL enable/disable functionsGravatar Jesse Barnes 1-0/+1
2011-01-19drm/i915: add pipe/plane enable/disable functionsGravatar Jesse Barnes 1-2/+3
2011-01-18drm/i915: make the blitter report buffer modifications to the FBC unitGravatar Jesse Barnes 1-0/+4
2011-01-18drm/i915: set more FBC chicken bitsGravatar Jesse Barnes 1-0/+2
2011-01-11drm/i915: detect & report PCH display error interruptsGravatar Jesse Barnes 1-0/+29
2011-01-11drm/i915: re-enable rc6 support for Ironlake+Gravatar Jesse Barnes 1-3/+47
2011-01-11drm/i915: Mask USER interrupts on gen6 (until required)Gravatar Chris Wilson 1-0/+1
2011-01-11drm/i915: support low power watermarks on IronlakeGravatar Jesse Barnes 1-0/+5
2011-01-11drm/i915: support overclocking on Sandy BridgeGravatar Jesse Barnes 1-0/+1
2011-01-11drm/i915: fix calculation of eDP signal levels on SandybridgeGravatar Yuanhan Liu 1-4/+5
2011-01-05Merge branch 'master' of /home/airlied/kernel/linux-2.6 into drm-core-nextGravatar Dave Airlie 1-0/+10
2010-12-23drm/i915: Verify Ironlake eDP presence on DP_A using the capability fuseGravatar Chris Wilson 1-0/+7
2010-12-23drm/i915: Set the required VFMUNIT clock gating disable on Ironlake.Gravatar Eric Anholt 1-0/+3
2010-12-18drm/i915: dynamic render p-state support for Sandy BridgeGravatar Jesse Barnes 1-1/+7
2010-12-16drm/i915: Add support for precise vblank timestamping (v2)Gravatar Mario Kleiner 1-0/+1
2010-12-15drm/i915: Add frame buffer compression on SandybridgeGravatar Yuanhan Liu 1-0/+10
2010-12-15drm/i915: Add self-refresh support on SandybridgeGravatar Yuanhan Liu 1-0/+40
2010-12-09drm/i915: Enable RC6 autodownclocking on SandybridgeGravatar Chris Wilson 1-0/+59
2010-12-09drm/i915: Terminate the FORCE WAKE after we have finished readingGravatar Chris Wilson 1-0/+1
2010-12-05drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBGravatar Chris Wilson 1-1/+18
2010-12-05drm/i915: Enable CB tuning of the Display PLLGravatar Chris Wilson 1-0/+1
2010-12-02Merge branch 'drm-intel-fixes' into drm-intel-nextGravatar Chris Wilson 1-0/+1
2010-12-02drm/i915: Always set the DP transcoder config to 8BPC.Gravatar Eric Anholt 1-0/+1
2010-11-25drm/i915: Add a mechanism for pipelining fence register updatesGravatar Daniel Vetter 1-1/+7
2010-11-22drm/i915: Add support for GPU reset on gen6.Gravatar Eric Anholt 1-0/+6
2010-11-22drm/i915: Capture interesting display registers on errorGravatar Chris Wilson 1-1/+5
2010-11-11drm/i915: Remove the definitions for Primary Ring BufferGravatar Chris Wilson 1-4/+6
2010-11-11drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring registerGravatar Zou Nan hai 1-0/+1
2010-11-08drm/i915: Apply display workaround required according to the B-Spec.Gravatar Eric Anholt 1-0/+2
2010-11-08drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.Gravatar Eric Anholt 1-0/+13
2010-10-29drm/i915: Record BSD engine error stateGravatar Chris Wilson 1-0/+4
2010-10-29drm/i915: Record BLT engine error stateGravatar Chris Wilson 1-0/+4
2010-10-27drm/i915: Capture ERROR register on Sandybridge hangsGravatar Chris Wilson 1-0/+2
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