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path: root/drivers/gpu/drm/i915/intel_dpio_phy.c
AgeCommit message (Expand)AuthorFilesLines
2016-11-02drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequenceGravatar Ander Conselvan de Oliveira 1-21/+0
2016-10-28drm/i915: Address broxton phy registers based on phy and channel numberGravatar Ander Conselvan de Oliveira 1-14/+54
2016-10-28drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_infoGravatar Ander Conselvan de Oliveira 1-17/+55
2016-10-28drm/i915: Create a struct to hold information about the broxton physGravatar Ander Conselvan de Oliveira 1-10/+55
2016-10-28drm/i915: Move broxton vswing sequence to intel_dpio_phy.cGravatar Ander Conselvan de Oliveira 1-0/+39
2016-10-28drm/i915: Move DPIO phy documentation section to intel_dpio_phy.cGravatar Ander Conselvan de Oliveira 1-0/+91
2016-10-28drm/i915: Move broxton phy code to intel_dpio_phy.cGravatar Ander Conselvan de Oliveira 1-0/+327
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Gravatar Chris Wilson 1-5/+5
2016-04-29drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.cGravatar Ander Conselvan de Oliveira 1-0/+15
2016-04-29drm/i915: Unduplicate pre encoder enabling phy codeGravatar Ander Conselvan de Oliveira 1-0/+30
2016-04-29drm/i915: Unduplicate VLV phy pre pll enabling codeGravatar Ander Conselvan de Oliveira 1-0/+28
2016-04-29drm/i915: Unduplicate VLV signal level codeGravatar Ander Conselvan de Oliveira 1-0/+26
2016-04-29drm/i915: Unduplicate CHV encoders' post pll disable codeGravatar Ander Conselvan de Oliveira 1-0/+33
2016-04-29drm/i915: Unduplicate CHV pre-encoder enabling phy logicGravatar Ander Conselvan de Oliveira 1-0/+92
2016-04-29drm/i915: Unduplicate CHV phy-releated pre pll enabling codeGravatar Ander Conselvan de Oliveira 1-0/+81
2016-04-29drm/i915: Unduplicate chv_data_lane_soft_reset()Gravatar Ander Conselvan de Oliveira 1-0/+43
2016-04-29drm/i915: Unduplicate CHV signal level codeGravatar Ander Conselvan de Oliveira 1-0/+122