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path: root/drivers/irqchip/irq-sifive-plic.c
AgeCommit message (Expand)AuthorFilesLines
2024-06-03irqchip/sifive-plic: Chain to parent IRQ after handlers are readyGravatar Samuel Holland 1-17/+17
2024-04-24irqchip/sifive-plic: Avoid explicit cpumask allocation on stackGravatar Dawei Li 1-5/+2
2024-03-11Merge tag 'irq-msi-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/g...Gravatar Linus Torvalds 1-105/+170
2024-02-23irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestoreGravatar Anup Patel 1-6/+10
2024-02-23irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_pr...Gravatar Anup Patel 1-10/+33
2024-02-23irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failureGravatar Anup Patel 1-20/+53
2024-02-23irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnodeGravatar Anup Patel 1-4/+5
2024-02-23irqchip/sifive-plic: Use devm_xyz() for managed allocationGravatar Anup Patel 1-33/+16
2024-02-23irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()Gravatar Anup Patel 1-11/+11
2024-02-23irqchip/sifive-plic: Convert PLIC driver into a platform driverGravatar Anup Patel 1-40/+61
2024-02-19irqchip/sifive-plic: Enable interrupt if needed before EOIGravatar Nam Cao 1-1/+7
2023-10-27irqchip/sifive-plic: Fix syscore registration for multi-socket systemsGravatar Anup Patel 1-3/+4
2023-04-08irqchip/irq-sifive-plic: Add syscore callbacks for hibernationGravatar Mason Huo 1-2/+91
2022-11-28irqchip/sifive-plic: Support wake IRQsGravatar Samuel Holland 1-2/+4
2022-08-06Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Gravatar Linus Torvalds 1-3/+4
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Gravatar Sunil V L 1-3/+4
2022-07-10irqchip/sifive-plic: Separate the enable and mask operationsGravatar Samuel Holland 1-21/+34
2022-07-10irqchip/sifive-plic: Make better use of the effective affinity maskGravatar Samuel Holland 1-18/+9
2022-07-01irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handlingGravatar Samuel Holland 1-1/+1
2022-07-01irqchip/sifive-plic: Add support for Renesas RZ/Five SoCGravatar Lad Prabhakar 1-4/+74
2022-03-14Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz...Gravatar Thomas Gleixner 1-12/+26
2022-03-02irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeGravatar Niklas Cassel 1-5/+19
2022-03-02irqchip/sifive-plic: Improve naming scheme for per context offsetsGravatar Niklas Cassel 1-7/+7
2022-02-02irqchip/sifive-plic: Add missing thead,c900-plic match stringGravatar Guo Ren 1-0/+1
2021-11-12irqchip/sifive-plic: Fixup EOI failed when maskedGravatar Guo Ren 1-1/+7
2021-06-10irqchip: Bulk conversion to generic_handle_domain_irq()Gravatar Marc Zyngier 1-5/+3
2021-04-07irqchip/sifive-plic: Mark two global variables __ro_after_initGravatar Jisheng Zhang 1-2/+2
2020-11-01irqchip/sifive-plic: Fix chip_data access within a hierarchyGravatar Greentime Hu 1-4/+4
2020-10-25irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGravatar Greentime Hu 1-1/+1
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverGravatar Anup Patel 1-9/+23
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryGravatar Anup Patel 1-15/+1
2020-05-25irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesGravatar Anup Patel 1-2/+2
2020-05-25irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentGravatar Anup Patel 1-2/+12
2020-05-25irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Gravatar Anup Patel 1-0/+3
2020-05-18irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsGravatar Wesley W. Terpstra 1-2/+0
2020-04-17irqchip/sifive-plic: Fix maximum priority threshold valueGravatar Atish Patra 1-1/+1
2020-03-16irqchip/sifive-plic: Add support for multiple PLICsGravatar Atish Patra 1-30/+51
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineGravatar Atish Patra 1-4/+34
2020-01-24Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...Gravatar Thomas Gleixner 1-4/+26
2020-01-20irqchip/sifive-plic: Support irq domain hierarchyGravatar Yash Shah 1-4/+26
2020-01-04riscv: prefix IRQ_ macro names with an RV_ namespaceGravatar Paul Walmsley 1-1/+1
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeGravatar Christoph Hellwig 1-4/+7
2019-10-25Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...Gravatar Thomas Gleixner 1-2/+2
2019-10-25irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Gravatar Alan Mikhak 1-2/+2
2019-10-14Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...Gravatar Thomas Gleixner 1-14/+15
2019-09-18irqchip/sifive-plic: Switch to fasteoi flowGravatar Marc Zyngier 1-14/+15
2019-09-05irqchip/sifive-plic: set max threshold for ignored handlersGravatar Christoph Hellwig 1-2/+10
2019-02-21irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostGravatar Anup Patel 1-6/+39
2019-02-21irqchip/sifive-plic: Differentiate between PLIC handler and contextGravatar Anup Patel 1-8/+8
2019-02-21irqchip/sifive-plic: Add warning in plic_init() if handler already presentGravatar Anup Patel 1-0/+5
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