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2020-12-15Merge tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafa...Gravatar Linus Torvalds 1-2/+1
2020-12-15Merge tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/brooni...Gravatar Linus Torvalds 1-2/+3
2020-12-15Merge tag 'net-next-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ne...Gravatar Linus Torvalds 1-0/+1
2020-12-14Merge tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mc...Gravatar Linus Torvalds 238-7944/+23754
2020-12-14Merge branch 'opp/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/gi...Gravatar Rafael J. Wysocki 1-2/+1
2020-12-14Merge tag 'drm-next-2020-12-11' of git://anongit.freedesktop.org/drm/drmGravatar Linus Torvalds 3-17/+40
2020-12-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netGravatar Jakub Kicinski 7-32/+58
2020-12-10Merge series "spi: spi-geni-qcom: Use gpio descriptors for CS" from Stephen B...Gravatar Mark Brown 34-984/+2415
2020-12-09media: venus: dev_pm_opp_put_*() accepts NULL argumentGravatar Viresh Kumar 1-2/+1
2020-12-08media: vidtv: fix some warningsGravatar Mauro Carvalho Chehab 3-3/+5
2020-12-07media: ccs: Add support for obtaining C-PHY configuration from firmwareGravatar Sakari Ailus 1-0/+4
2020-12-07media: ccs-pll: Print pixel ratesGravatar Sakari Ailus 1-0/+5
2020-12-07media: ccs: Print written register valuesGravatar Sakari Ailus 1-0/+4
2020-12-07media: ccs: Add support for DDR OP SYS and OP PIX clocksGravatar Sakari Ailus 1-1/+8
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksGravatar Sakari Ailus 2-20/+46
2020-12-07media: ccs: Dual PLL supportGravatar Sakari Ailus 2-3/+51
2020-12-07media: ccs-pll: Add trivial dual PLL supportGravatar Sakari Ailus 2-22/+196
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restGravatar Sakari Ailus 1-27/+37
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationGravatar Sakari Ailus 1-5/+7
2020-12-07media: ccs-pll: Make VT divisors 16-bitGravatar Sakari Ailus 1-26/+25
2020-12-07media: ccs-pll: Rework bounds checksGravatar Sakari Ailus 2-57/+95
2020-12-07media: ccs-pll: Print relevant information on PLL treeGravatar Sakari Ailus 1-19/+66
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationGravatar Sakari Ailus 1-23/+31
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsGravatar Sakari Ailus 3-29/+64
2020-12-07media: ccs-pll: Split off VT subtree calculationGravatar Sakari Ailus 1-124/+131
2020-12-07media: ccs-pll: Add C-PHY supportGravatar Sakari Ailus 1-9/+26
2020-12-07media: ccs-pll: Add sanity checksGravatar Sakari Ailus 1-0/+9
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerGravatar Sakari Ailus 3-8/+23
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainGravatar Sakari Ailus 3-6/+16
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerGravatar Sakari Ailus 3-1/+7
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationGravatar Sakari Ailus 4-19/+23
2020-12-07media: ccs: Add support for lane speed modelGravatar Sakari Ailus 1-1/+10
2020-12-07media: ccs-pll: Add support for lane speed modelGravatar Sakari Ailus 2-11/+31
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeGravatar Sakari Ailus 1-2/+2
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundGravatar Sakari Ailus 1-2/+1
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierGravatar Sakari Ailus 1-1/+1
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchGravatar Sakari Ailus 1-2/+9
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundGravatar Sakari Ailus 1-1/+1
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencyGravatar Sakari Ailus 1-8/+4
2020-12-07media: ccs-pll: Use the BIT macroGravatar Sakari Ailus 1-2/+5
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionGravatar Sakari Ailus 1-0/+89
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsGravatar Sakari Ailus 1-1/+1
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYGravatar Sakari Ailus 3-3/+4
2020-12-07media: ccs-pll: Remove parallel bus supportGravatar Sakari Ailus 2-15/+4
2020-12-07media: ccs-pll: End search if there are no better values availableGravatar Sakari Ailus 1-2/+8
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorGravatar Sakari Ailus 1-2/+2
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsGravatar Sakari Ailus 3-188/+209
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberGravatar Sakari Ailus 1-1/+1
2020-12-07media: netup_unidvb: Don't leak SPI master in probe error pathGravatar Lukas Wunner 1-2/+3
2020-12-07media: vivid: fix 'disconnect' error injectionGravatar Hans Verkuil 3-30/+66
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