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path: root/drivers/phy/cadence
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2024-02-07phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink...Gravatar Swapnil Jakhade 1-0/+410
2024-02-07phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink...Gravatar Swapnil Jakhade 1-0/+101
2024-02-07phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configu...Gravatar Swapnil Jakhade 1-9/+200
2023-07-17phy: Explicitly include correct DT includesGravatar Rob Herring 3-4/+2
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationGravatar Marcin Wierzbicki 1-0/+98
2023-07-12phy: cadence-torrent: Use key:value pair table for all settingsGravatar Roger Quadros 1-1176/+485
2023-07-12phy: cadence-torrent: Add single link USXGMII configuration for 156.25MHz refclkGravatar Swapnil Jakhade 1-5/+228
2023-07-05Merge tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Gravatar Linus Torvalds 2-202/+613
2023-06-08phy: cadence: torrent: Add a determine_rate hookGravatar Maxime Ripard 1-0/+1
2023-06-08phy: cadence: sierra: Add a determine_rate hookGravatar Maxime Ripard 1-0/+1
2023-05-19phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt propertyGravatar Frank Li 1-0/+29
2023-05-19phy: cadence: salvo: add .set_mode APIGravatar Peter Chen 1-0/+29
2023-05-19phy: cadence: salvo: add bist fixGravatar Peter Chen 1-0/+2
2023-05-19phy: cadence: salvo: decrease delay value to zero for txvalidGravatar Peter Chen 1-0/+17
2023-05-19phy: cadence: salvo: add access for USB2PHYGravatar Peter Chen 1-8/+10
2023-05-08phy: cadence-torrent: Add USB + DP multilink configurationGravatar Swapnil Jakhade 1-0/+98
2023-05-08phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclkGravatar Swapnil Jakhade 1-57/+227
2023-05-08phy: cadence-torrent: Prepare driver for multilink DP supportGravatar Swapnil Jakhade 1-137/+168
2023-05-08phy: cadence-torrent: Add function to get PLL to be configured for DPGravatar Swapnil Jakhade 1-0/+33
2023-04-12phy: cadence: cdns-dphy-rx: Add common module reset supportGravatar Sinthu Raja 1-0/+32
2023-04-12phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configurationGravatar Swapnil Jakhade 1-2/+139
2023-03-31phy: cadence: Sierra: Use clk_parent_data to provide parent informationGravatar Lars-Peter Clausen 1-42/+15
2023-03-31phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`Gravatar Lars-Peter Clausen 1-20/+26
2023-03-20phy: cadence: phy-cadence-torrent: Convert to platform remove callback return...Gravatar Uwe Kleine-König 1-4/+2
2023-03-20phy: cadence: phy-cadence-sierra: Convert to platform remove callback returni...Gravatar Uwe Kleine-König 1-4/+2
2023-03-20phy: cadence: cdns-dphy: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
2022-07-08phy: cadence-torrent: Remove unused `regmap` field from state structGravatar Lars-Peter Clausen 1-1/+0
2022-07-08phy: cadence: Sierra: Remove unused `regmap` field from state structGravatar Lars-Peter Clausen 1-1/+0
2022-07-05phy: cdns-dphy: Add support for DPHY TX on J721eGravatar Rahul T R 1-0/+61
2022-07-05phy: cdns-dphy: Add band config for dphy txGravatar Rahul T R 1-1/+39
2022-04-13phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationGravatar Swapnil Jakhade 1-3/+190
2022-03-02phy: cadence: Add Cadence D-PHY Rx driverGravatar Pratyush Yadav 3-0/+264
2022-02-25phy/cadence: Use of_device_get_match_data()Gravatar Minghao Chi (CGEL ZTE) 1-6/+1
2022-02-07phy: cadence: Sierra: Add support for skipping configurationGravatar Aswath Govindraju 1-25/+57
2022-01-24phy: cadence: Sierra: fix error handling bugs in probe()Gravatar Dan Carpenter 1-14/+21
2021-12-27phy: cadence: Sierra: Add support for derived reference clock outputGravatar Swapnil Jakhade 1-1/+108
2021-12-27phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationGravatar Swapnil Jakhade 1-1/+376
2021-12-27phy: cadence: Sierra: Add support for PHY multilink configurationsGravatar Swapnil Jakhade 1-8/+190
2021-12-27phy: cadence: Sierra: Fix to get correct parent for mux clocksGravatar Swapnil Jakhade 1-5/+26
2021-12-27phy: cadence: Sierra: Update single link PCIe register configurationGravatar Swapnil Jakhade 1-1/+213
2021-12-27phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationGravatar Swapnil Jakhade 1-1/+72
2021-12-27phy: cadence: Sierra: Check cmn_ready assertion during PHY power onGravatar Swapnil Jakhade 1-0/+45
2021-12-27phy: cadence: Sierra: Add PHY PCS common register configurationsGravatar Swapnil Jakhade 1-0/+38
2021-12-27phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...Gravatar Swapnil Jakhade 1-10/+11
2021-12-27phy: cadence: Sierra: Add support to get SSC type from device treeGravatar Swapnil Jakhade 1-1/+5
2021-12-27phy: cadence: Sierra: Prepare driver to add support for multilink configurationsGravatar Swapnil Jakhade 1-56/+139
2021-12-27phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataGravatar Swapnil Jakhade 1-9/+4
2021-11-23phy: cadence-torrent: use swap() to make code cleanerGravatar Yang Guang 1-4/+2
2021-10-26phy: cadence-torrent: Add support to output received reference clockGravatar Swapnil Jakhade 1-11/+148
2021-10-26phy: cadence-torrent: Model reference clock driver as a clock to enable deriv...Gravatar Swapnil Jakhade 1-25/+132