linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author	Files	Lines
2022-05-19	cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()	Dan Williams	3	-16/+5
2022-05-19	cxl/mem: Consolidate CXL DVSEC Range enumeration in the core	Dan Williams	3	-10/+17
2022-05-19	cxl/pci: Move cxl_await_media_ready() to the core	Dan Williams	3	-7/+16
2022-04-12	cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()	Dan Williams	1	-1/+1
2022-02-08	tools/testing/cxl: Add a physical_node link	Dan Williams	1	-2/+19
2022-02-08	tools/testing/cxl: Enumerate mock decoders	Dan Williams	1	-20/+98
2022-02-08	tools/testing/cxl: Mock one level of switches	Dan Williams	1	-41/+97
2022-02-08	tools/testing/cxl: Fix root port to host bridge assignment	Dan Williams	1	-1/+1
2022-02-08	tools/testing/cxl: Mock dvsec_ranges()	Dan Williams	1	-0/+10
2022-02-08	cxl/mem: Add the cxl_mem driver	Ben Widawsky	2	-0/+16
2022-02-08	cxl/memdev: Add numa_node attribute	Dan Williams	1	-0/+1
2022-02-08	cxl/pci: Emit device serial number	Dan Williams	1	-0/+1
2022-02-08	cxl/pci: Implement wait for media active	Ben Widawsky	1	-0/+8
2022-02-08	cxl/core/port: Remove @host argument for dport + decoder enumeration	Dan Williams	3	-30/+21
2022-02-08	cxl/port: Add a driver for 'struct cxl_port' objects	Ben Widawsky	2	-2/+5
2022-02-08	cxl/core/hdm: Add CXL standard decoder enumeration to the core	Dan Williams	4	-0/+86
2022-02-08	cxl/core: Generalize dport enumeration in the core	Dan Williams	5	-128/+71
2022-02-08	cxl/port: Up-level cxl_add_dport() locking requirements to the caller	Dan Williams	1	-0/+4
2022-02-08	cxl/pmem: Introduce a find_cxl_root() helper	Dan Williams	2	-26/+0
2022-02-08	cxl/core/port: Rename bus.c to port.c	Dan Williams	1	-1/+1
2021-11-15	cxl/test: Mock acpi_table_parse_cedt()	Dan Williams	4	-48/+59
2021-11-15	tools/testing/cxl: add mock output for the GET_HEALTH_INFO command	Vishal Verma	1	-0/+49
2021-11-15	cxl/memdev: Change cxl_mem to a more descriptive name	Ira Weiny	1	-25/+25
2021-09-21	tools/testing/cxl: Introduce a mock memory device + driver	Dan Williams	5	-1/+354
2021-09-21	tools/testing/cxl: Introduce a mocked-up CXL port hierarchy	Dan Williams	7	-0/+871