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path: root/tools/testing/cxl
AgeCommit message (Expand)AuthorFilesLines
2022-11-04tools/testing/cxl: Add a single-port host-bridge regression configGravatar Dan Williams 1-19/+278
2022-11-04tools/testing/cxl: Fix some error exitsGravatar Dan Williams 1-2/+2
2022-07-25cxl/hdm: Commit decoder state to hardwareGravatar Dan Williams 1-0/+46
2022-07-21cxl/region: Add region creation supportGravatar Ben Widawsky 1-0/+1
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Gravatar Dan Williams 1-3/+7
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Gravatar Dan Williams 1-7/+16
2022-07-10tools/testing/cxl: Fix decoder default stateGravatar Dan Williams 1-1/+0
2022-07-10tools/testing/cxl: Add partition supportGravatar Dan Williams 2-63/+28
2022-07-10tools/testing/cxl: Expand CFMWS windowsGravatar Dan Williams 1-5/+5
2022-07-10tools/testing/cxl: Move cxl_test resources to the top of memoryGravatar Dan Williams 1-1/+2
2022-07-09cxl/mem: Convert partition-info to resourcesGravatar Dan Williams 1-1/+1
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeGravatar Dan Williams 1-1/+1
2022-06-28tools/testing/cxl: Fix cxl_hdm_decode_init() calling conventionGravatar Dan Williams 1-3/+5
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initGravatar Dan Williams 1-2/+3
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Gravatar Dan Williams 1-6/+3
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Gravatar Dan Williams 3-16/+5
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreGravatar Dan Williams 3-10/+17
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreGravatar Dan Williams 3-7/+16
2022-04-12cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()Gravatar Dan Williams 1-1/+1
2022-02-08tools/testing/cxl: Add a physical_node linkGravatar Dan Williams 1-2/+19
2022-02-08tools/testing/cxl: Enumerate mock decodersGravatar Dan Williams 1-20/+98
2022-02-08tools/testing/cxl: Mock one level of switchesGravatar Dan Williams 1-41/+97
2022-02-08tools/testing/cxl: Fix root port to host bridge assignmentGravatar Dan Williams 1-1/+1
2022-02-08tools/testing/cxl: Mock dvsec_ranges()Gravatar Dan Williams 1-0/+10
2022-02-08cxl/mem: Add the cxl_mem driverGravatar Ben Widawsky 2-0/+16
2022-02-08cxl/memdev: Add numa_node attributeGravatar Dan Williams 1-0/+1
2022-02-08cxl/pci: Emit device serial numberGravatar Dan Williams 1-0/+1
2022-02-08cxl/pci: Implement wait for media activeGravatar Ben Widawsky 1-0/+8
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationGravatar Dan Williams 3-30/+21
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsGravatar Ben Widawsky 2-2/+5
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreGravatar Dan Williams 4-0/+86
2022-02-08cxl/core: Generalize dport enumeration in the coreGravatar Dan Williams 5-128/+71
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerGravatar Dan Williams 1-0/+4
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperGravatar Dan Williams 2-26/+0
2022-02-08cxl/core/port: Rename bus.c to port.cGravatar Dan Williams 1-1/+1
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Gravatar Dan Williams 4-48/+59
2021-11-15tools/testing/cxl: add mock output for the GET_HEALTH_INFO commandGravatar Vishal Verma 1-0/+49
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameGravatar Ira Weiny 1-25/+25
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverGravatar Dan Williams 5-1/+354
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyGravatar Dan Williams 7-0/+871
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