aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/rda8810pl.dtsi
blob: f30d6ece49fb33d9c5c3ad9522c83bb8e4f8b488 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * RDA8810PL SoC
 *
 * Copyright (c) 2017 Andreas Färber
 * Copyright (c) 2018 Manivannan Sadhasivam
 */

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "rda,8810pl";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0x0>;
		};
	};

	sram@100000 {
		compatible = "mmio-sram";
		reg = <0x100000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
	};

	modem@10000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x10000000 0xfffffff>;

		gpioc@1a08000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x1a08000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
		};
	};

	apb@20800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20800000 0x100000>;

		intc: interrupt-controller@0 {
			compatible = "rda,8810pl-intc";
			reg = <0x0 0x1000>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	apb@20900000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20900000 0x100000>;

		timer@10000 {
			compatible = "rda,8810pl-timer";
			reg = <0x10000 0x1000>;
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
				     <17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hwtimer", "ostimer";
		};

		gpioa@30000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x30000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
		};

		gpiob@31000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x31000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
		};

		gpiod@32000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x32000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	apb@20a00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20a00000 0x100000>;

		uart1: serial@0 {
			compatible = "rda,8810pl-uart";
			reg = <0x0 0x1000>;
			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: serial@10000 {
			compatible = "rda,8810pl-uart";
			reg = <0x10000 0x1000>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: serial@90000 {
			compatible = "rda,8810pl-uart";
			reg = <0x90000 0x1000>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};
	};

	l2: cache-controller@21100000 {
		compatible = "arm,pl310-cache";
		reg = <0x21100000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};
};