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| author |  Michal Wajdeczko <michal.wajdeczko@intel.com>
| 2023-12-18 17:53:37 +0100 |
|---|---|---|
| committer |  Rodrigo Vivi <rodrigo.vivi@intel.com>
| 2023-12-21 16:31:29 -0500 |
| commit | e3408839dd27b2645636f91c85a7fd847e36cb91 (patch) | |
| tree | 3853281e36959cbf0834a6740598d70773735cca | |
| parent | drm/xe: Define registers used by memory based irq processing (diff) | |
| download | linux-e3408839dd27b2645636f91c85a7fd847e36cb91.tar.gz linux-e3408839dd27b2645636f91c85a7fd847e36cb91.tar.bz2 linux-e3408839dd27b2645636f91c85a7fd847e36cb91.zip | |
drm/xe: Update LRC context layout definitions
The new memory based interrupt processing uses additional entries
in the context. Add required definitions.
Bspec: 45585, 60184
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-4-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_lrc_layout.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h index 4be81abc86ad..1825d8f79db6 100644 --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h @@ -14,4 +14,13 @@ #define CTX_PDP0_UDW (0x30 + 1) #define CTX_PDP0_LDW (0x32 + 1) +#define CTX_LRM_INT_MASK_ENABLE 0x50 +#define CTX_INT_MASK_ENABLE_REG (CTX_LRM_INT_MASK_ENABLE + 1) +#define CTX_INT_MASK_ENABLE_PTR (CTX_LRM_INT_MASK_ENABLE + 2) +#define CTX_LRI_INT_REPORT_PTR 0x55 +#define CTX_INT_STATUS_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 1) +#define CTX_INT_STATUS_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 2) +#define CTX_INT_SRC_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 3) +#define CTX_INT_SRC_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 4) + #endif |