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| author |  Heiko Stuebner <heiko@sntech.de>
| 2022-05-11 21:29:11 +0200 |
|---|---|---|
| committer |  Palmer Dabbelt <palmer@rivosinc.com>
| 2022-05-11 21:36:31 -0700 |
| commit | d14ca1f8d3039970e812fec1f01e7b46b62cc5fc (patch) | |
| tree | d71e6034b692fd44af4188941af5174d54871705 /arch/riscv/errata | |
| parent | riscv: integrate alternatives better into the main architecture (diff) | |
| download | linux-d14ca1f8d3039970e812fec1f01e7b46b62cc5fc.tar.gz linux-d14ca1f8d3039970e812fec1f01e7b46b62cc5fc.tar.bz2 linux-d14ca1f8d3039970e812fec1f01e7b46b62cc5fc.zip | |
riscv: allow different stages with alternatives
Future features may need to be applied at a different
time during boot, so allow defining stages for alternatives
and handling them differently depending on the stage.
Also make the alternatives-location more flexible so that
future stages may provide their own location.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Link: https://lore.kernel.org/r/20220511192921.2223629-3-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/errata')
| -rw-r--r-- | arch/riscv/errata/sifive/errata.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index f5e5ae70e829..4fe03ac41fd7 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -80,7 +80,8 @@ static void __init warn_miss_errata(u32 miss_errata) } void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, - unsigned long archid, unsigned long impid) + unsigned long archid, unsigned long impid, + unsigned int stage) { struct alt_entry *alt; u32 cpu_req_errata = sifive_errata_probe(archid, impid); |