aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv/errata
AgeCommit message (Expand)AuthorFilesLines
2024-05-22Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...Gravatar Linus Torvalds 1-0/+5
2024-04-29riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Gravatar Samuel Holland 1-0/+5
2024-04-26Merge patch series "RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE"Gravatar Palmer Dabbelt 1-9/+15
2024-04-25riscv: T-Head: Test availability bit before enabling MAE errataGravatar Christoph Müllner 1-4/+10
2024-04-25riscv: thead: Rename T-Head PBMT to MAEGravatar Christoph Müllner 1-5/+5
2024-03-12riscv: errata: Rename defines for AndesGravatar Yu Chien Peter Lin 1-5/+5
2024-01-11Merge patch series "riscv: errata: thead: use riscv_nonstd_cache_ops for CMO"Gravatar Palmer Dabbelt 1-2/+67
2024-01-10riscv: errata: thead: use pa based instructions for CMOGravatar Jisheng Zhang 1-12/+6
2024-01-10riscv: errata: thead: use riscv_nonstd_cache_ops for CMOGravatar Jisheng Zhang 1-2/+73
2023-12-06riscv: errata: andes: Probe for IOCP only once in boot stageGravatar Lad Prabhakar 1-7/+13
2023-09-27riscv: errata: andes: Makefile: Fix randconfig build issueGravatar Lad Prabhakar 1-0/+4
2023-09-08Merge patch series "Add non-coherent DMA support for AX45MP"Gravatar Palmer Dabbelt 3-0/+68
2023-09-01riscv: errata: Add Andes alternative portsGravatar Lad Prabhakar 3-0/+68
2023-09-01RISC-V: alternative: Remove feature_probe_funcGravatar Evan Green 1-8/+0
2023-07-06Merge patch series "riscv: some CMO alternative related clean up"Gravatar Palmer Dabbelt 1-2/+5
2023-07-06riscv: errata: thead: only set cbom size & noncoherent during bootGravatar Jisheng Zhang 1-2/+5
2023-05-31riscv: Fix relocatable kernels with early alternatives using -fno-pieGravatar Alexandre Ghiti 1-0/+4
2023-04-29RISC-V: fix sifive and thead section mismatches in errataGravatar Randy Dunlap 2-8/+6
2023-04-28Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Gravatar Linus Torvalds 2-6/+16
2023-04-25RISC-V: hwprobe: Remove __init on probe_vendor_features()Gravatar Evan Green 1-3/+3
2023-04-18Merge patch series "RISC-V Hardware Probing User Interface"Gravatar Palmer Dabbelt 1-0/+10
2023-04-18RISC-V: hwprobe: Support probing of misaligned access performanceGravatar Evan Green 1-0/+10
2023-03-14riscv: alternatives: Rename errata_id to patch_idGravatar Andrew Jones 2-5/+5
2023-03-14riscv: alternatives: Remove unnecessary define and unused structGravatar Andrew Jones 1-1/+1
2023-03-07RISC-V: fix taking the text_mutex twice during sifive errata patchingGravatar Conor Dooley 1-1/+1
2023-02-21RISC-V: take text_mutex during alternative patchingGravatar Conor Dooley 2-2/+9
2023-02-14riscv: Fix early alternative patchingGravatar Samuel Holland 1-3/+1
2023-01-31riscv: switch to relative alternative entriesGravatar Jisheng Zhang 2-4/+10
2022-10-27drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx coresGravatar Heiko Stuebner 1-0/+19
2022-10-13Merge patch series "Some style cleanups for recent extension additions"Gravatar Palmer Dabbelt 1-6/+8
2022-10-13riscv: check for kernel config option in t-head memory types errataGravatar Heiko Stuebner 1-0/+3
2022-10-13riscv: use BIT() macros in t-head errata initGravatar Heiko Stuebner 1-2/+2
2022-10-13riscv: drop some idefs from CMO initializationGravatar Heiko Stuebner 1-4/+3
2022-09-13RISC-V: Clean up the Zicbom block size probingGravatar Palmer Dabbelt 1-0/+1
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantGravatar Palmer Dabbelt 1-0/+20
2022-08-06Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Gravatar Linus Torvalds 1-26/+12
2022-08-03riscv: implement cache-management errata for T-Head SoCsGravatar Heiko Stuebner 1-0/+20
2022-07-07riscv: don't warn for sifive erratas in modulesGravatar Heiko Stuebner 1-1/+2
2022-06-16riscv: remove usage of function-pointers from cpufeatures and t-head errataGravatar Heiko Stuebner 1-26/+12
2022-05-11riscv: add memory-type errata for T-HeadGravatar Heiko Stuebner 4-1/+100
2022-05-11riscv: implement module alternativesGravatar Heiko Stuebner 1-5/+9
2022-05-11riscv: allow different stages with alternativesGravatar Heiko Stuebner 1-1/+2
2022-05-11riscv: integrate alternatives better into the main architectureGravatar Heiko Stuebner 2-76/+0
2022-01-09riscv: errata: alternative: mark vendor_patch_func __initdataGravatar Jisheng Zhang 1-1/+2
2021-06-01riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledGravatar Vincent 1-1/+1
2021-04-26riscv: sifive: Apply errata "cip-1200" patchGravatar Vincent Chen 1-0/+18
2021-04-26riscv: sifive: Apply errata "cip-453" patchGravatar Vincent Chen 3-0/+59
2021-04-26riscv: sifive: Add SiFive alternative portsGravatar Vincent Chen 4-0/+75
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionGravatar Vincent Chen 2-0/+70