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| author |  Minda Chen <minda.chen@starfivetech.com>
| 2023-08-02 14:42:15 +0800 |
|---|---|---|
| committer |  Palmer Dabbelt <palmer@rivosinc.com>
| 2023-10-31 19:15:54 -0700 |
| commit | dd16ac404a685cce07e67261a94c6225d90ea7ba (patch) | |
| tree | 807c05359bbe2743b8724c47fa5ac9fc7e733256 /arch/riscv/include | |
| parent | riscv/mm: Fix the comment for swap pte format (diff) | |
| download | linux-dd16ac404a685cce07e67261a94c6225d90ea7ba.tar.gz linux-dd16ac404a685cce07e67261a94c6225d90ea7ba.tar.bz2 linux-dd16ac404a685cce07e67261a94c6225d90ea7ba.zip | |
riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause
Actually it is a part of Conor's
commit aae538cd03bc ("riscv: fix detection of toolchain
Zihintpause support").
It is looks like a merge issue. Samuel's
commit 0b1d60d6dd9e ("riscv: Fix build with
CONFIG_CC_OPTIMIZE_FOR_SIZE=y") do not base on Conor's commit and
revert to __riscv_zihintpause. So this patch can fix it.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Fixes: 3c349eacc559 ("Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230802064215.31111-1-minda.chen@starfivetech.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/vdso/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h index 14f5d27783b8..96b65a5396df 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -14,7 +14,7 @@ static inline void cpu_relax(void) __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); #endif -#ifdef __riscv_zihintpause +#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE /* * Reduce instruction retirement. * This assumes the PC changes. |