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authorGravatar Samuel Holland <samuel@sholland.org> 2022-06-30 05:02:40 -0500
committerGravatar Marc Zyngier <maz@kernel.org> 2022-07-01 15:27:23 +0100
commitd60df7fd225af37e31859a9badb0cca73f7aa12d (patch)
treebd68ce1db282476746eb3d4d57d5f6e4b2c39f12 /drivers/irqchip/irq-sifive-plic.c
parentirqchip/sifive-plic: Add support for Renesas RZ/Five SoC (diff)
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dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC
The RISC-V PLIC specification unfortunately allows PLIC implementations to ignore edges seen while an edge-triggered interrupt is being handled: Depending on the design of the device and the interrupt handler, in between sending an interrupt request and receiving notice of its handler’s completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus it also needs to inform software about each interrupt's trigger type, so the driver can use the right interrupt flow. Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220630100241.35233-4-samuel@sholland.org
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