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2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Gravatar Linus Torvalds 40-336/+1599
2023-11-09Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...Gravatar Palmer Dabbelt 4-32/+20
2023-11-08Merge patch series "Linux RISC-V AIA Preparatory Series"Gravatar Palmer Dabbelt 1-5/+6
2023-11-08RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTsGravatar Anup Patel 1-5/+6
2023-11-08Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Gravatar Linus Torvalds 14-222/+275
2023-11-07RISC-V: Probe misaligned access speed in parallelGravatar Evan Green 2-20/+77
2023-11-07RISC-V: Remove __init on unaligned_emulation_finish()Gravatar Evan Green 1-1/+1
2023-11-07RISC-V: Show accurate per-hart isa in /proc/cpuinfoGravatar Evan Green 1-4/+18
2023-11-07RISC-V: Don't rely on positional structure initializationGravatar Palmer Dabbelt 1-60/+65
2023-11-07Merge patch series "riscv: Add remaining module relocations and tests"Gravatar Palmer Dabbelt 16-104/+864
2023-11-07riscv: Add tests for riscv module loadingGravatar Charlie Jenkins 15-0/+365
2023-11-07riscv: Add remaining module relocationsGravatar Charlie Jenkins 1-29/+419
2023-11-07riscv: Avoid unaligned access when relocating modulesGravatar Emil Renner Berthing 1-76/+81
2023-11-06riscv: kernel: Use correct SYM_DATA_*() macro for dataGravatar Clément Léger 1-5/+4
2023-11-06riscv: Use SYM_*() assembly macros instead of deprecated onesGravatar Clément Léger 12-48/+44
2023-11-06riscv: use ".L" local labels in assembly when applicableGravatar Clément Léger 3-17/+17
2023-11-06Merge patch series "riscv: tlb flush improvements"Gravatar Palmer Dabbelt 1-22/+10
2023-11-06riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbGravatar Alexandre Ghiti 1-22/+10
2023-11-05Merge patch series "riscv: vdso.lds.S: some improvement"Gravatar Palmer Dabbelt 1-17/+13
2023-11-05riscv: vdso.lds.S: remove hardcoded 0x800 .text start addrGravatar Jisheng Zhang 1-9/+8
2023-11-05riscv: vdso.lds.S: merge .data section into .rodata sectionGravatar Jisheng Zhang 1-8/+7
2023-11-05riscv: vdso.lds.S: drop __alt_start and __alt_end symbolsGravatar Jisheng Zhang 1-2/+0
2023-11-05riscv: add userland instruction dump to RISC-V splatsGravatar Yunhui Cui 1-3/+18
2023-11-05riscv: kprobes: allow writing to x0Gravatar Nam Cao 1-1/+1
2023-11-05riscv: provide riscv-specific is_trap_insn()Gravatar Nam Cao 1-0/+6
2023-11-05riscv: don't probe unaligned access speed if already doneGravatar Jisheng Zhang 1-0/+4
2023-11-05riscv: signal: handle syscall restart before get_signalGravatar Haorong Lu 1-39/+46
2023-11-05Merge patch series "Add support to handle misaligned accesses in S-mode"Gravatar Palmer Dabbelt 7-59/+474
2023-11-04Merge tag 'kbuild-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/masa...Gravatar Linus Torvalds 2-20/+0
2023-11-03Merge tag 'tty-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/greg...Gravatar Linus Torvalds 2-12/+2
2023-11-02Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmGravatar Linus Torvalds 1-0/+2
2023-11-02RISC-V: hwprobe: Fix vDSO SIGSEGVGravatar Andrew Jones 1-1/+1
2023-11-02Merge patch series "riscv: SCS support"Gravatar Palmer Dabbelt 7-171/+112
2023-11-01Merge tag 'sysctl-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/m...Gravatar Linus Torvalds 1-1/+0
2023-11-01Merge tag 'docs-6.7' of git://git.lwn.net/linuxGravatar Linus Torvalds 1-1/+1
2023-11-01riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNGravatar Clément Léger 2-0/+24
2023-11-01riscv: report misaligned accesses emulation to hwprobeGravatar Clément Léger 3-1/+61
2023-11-01riscv: annotate check_unaligned_access_boot_cpu() with __initGravatar Clément Léger 1-1/+1
2023-11-01riscv: add support for sysctl unaligned_enabled controlGravatar Clément Léger 1-0/+9
2023-11-01riscv: add floating point insn support to misaligned access emulationGravatar Clément Léger 2-4/+269
2023-11-01riscv: report perf event for misaligned faultGravatar Clément Léger 1-0/+5
2023-11-01riscv: add support for misaligned trap handling in S-modeGravatar Clément Léger 3-23/+107
2023-11-01riscv: remove unused functions in traps_misaligned.cGravatar Clément Léger 1-39/+7
2023-10-31Merge patch series "RISC-V: ACPI improvements"Gravatar Palmer Dabbelt 1-2/+85
2023-10-31riscv: put interrupt entries into .irqentry.textGravatar Nam Cao 1-0/+2
2023-10-31RISC-V: clarify the QEMU workaround in ISA parserGravatar Tsukasa OI 1-3/+4
2023-10-31Merge patch series "RISC-V: Enable cbo.zero in usermode"Gravatar Palmer Dabbelt 4-16/+48
2023-10-31Merge patch series "riscv: kexec: cleanup and fixups"Gravatar Palmer Dabbelt 2-30/+30
2023-10-31Merge tag 'kvm-riscv-6.7-1' of https://github.com/kvm-riscv/linux into HEADGravatar Paolo Bonzini 1-0/+2
2023-10-28kbuild: unify vdso_install rulesGravatar Masahiro Yamada 2-20/+0