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path: root/drivers/gpu/drm/i915/intel_psr.c
AgeCommit message (Expand)AuthorFilesLines
2016-12-20drm/i915: disable PSR by default on HSW/BDWGravatar Paulo Zanoni 1-7/+3
2016-11-17drm/i915: Assorted INTEL_INFO(dev) cleanupsGravatar Tvrtko Ursulin 1-2/+2
2016-11-11drm/i915: More assorted dev_priv cleanupsGravatar Tvrtko Ursulin 1-1/+1
2016-10-14drm/i915: Make IS_CHERRYVIEW only take dev_privGravatar Tvrtko Ursulin 1-2/+2
2016-10-14drm/i915: Make IS_HASWELL only take dev_privGravatar Tvrtko Ursulin 1-3/+3
2016-10-14drm/i915: Make IS_BROADWELL only take dev_privGravatar Tvrtko Ursulin 1-2/+2
2016-10-14drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_privGravatar Tvrtko Ursulin 1-4/+4
2016-09-13Revert "drm/i915/psr: Make idle_frames sensible again"Gravatar Rodrigo Vivi 1-7/+7
2016-08-15Merge tag 'drm-intel-next-2016-08-08' of git://anongit.freedesktop.org/drm-in...Gravatar Dave Airlie 1-15/+11
2016-08-04drm/i915: Use dev_priv consistently through the intel_frontbuffer interfaceGravatar Chris Wilson 1-15/+11
2016-08-03drm/i915: Check PSR setup time vs. vblank lengthGravatar Ville Syrjälä 1-1/+18
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Gravatar Chris Wilson 1-18/+18
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Gravatar Chris Wilson 1-4/+10
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Gravatar Chris Wilson 1-3/+5
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Gravatar Chris Wilson 1-2/+5
2016-05-20drm/i915/psr: Use ->get_aux_send_ctl functionsGravatar Daniel Vetter 1-21/+4
2016-05-20drm/i915/psr: Order DP aux transactions correctlyGravatar Daniel Vetter 1-7/+7
2016-05-20drm/i915/psr: Make idle_frames sensible againGravatar Daniel Vetter 1-7/+7
2016-05-20drm/i915/psr: Try to program link training times correctlyGravatar Daniel Vetter 1-8/+47
2016-04-07drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)Gravatar Joonas Lahtinen 1-1/+1
2016-03-10Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."Gravatar Ville Syrjälä 1-2/+1
2016-03-03drm/i915: Add wait_for_usGravatar Tvrtko Ursulin 1-1/+2
2016-02-17drm/i915: Enable PSR by default on Haswell and Broadwell.Gravatar Rodrigo Vivi 1-1/+2
2016-02-17drm/i915: Enable PSR by default on Valleyview and Cherryview.Gravatar Rodrigo Vivi 1-1/+4
2016-02-17drm/i915: Change i915.enable_psr parameter to use per platform default.Gravatar Rodrigo Vivi 1-0/+5
2016-02-01drm/i915: Instrument PSR parameter for debuging with link standby x link off.Gravatar Rodrigo Vivi 1-0/+17
2016-02-01drm/i915: Add PSR main link standby support backGravatar Rodrigo Vivi 1-7/+19
2016-02-01drm/i915: PSR simplify port and link standby checks.Gravatar Rodrigo Vivi 1-3/+10
2015-12-11drm/i915: PSR also doesn't have link_entry_time on SKL.Gravatar Rodrigo Vivi 1-2/+3
2015-12-10drm/i915: Separate cherryview from valleyviewGravatar Wayne Boyer 1-3/+3
2015-12-07drm/i915: Fix idle_frames counter.Gravatar Rodrigo Vivi 1-13/+7
2015-11-24drm/i915: Also disable PSR on Sink when disabling it on Source.Gravatar Rodrigo Vivi 1-0/+4
2015-11-24drm/i915: PSR: Mask LPSP hw tracking back again.Gravatar Rodrigo Vivi 1-2/+7
2015-11-24drm/i915: PSR: Let's rely more on frontbuffer tracking.Gravatar Rodrigo Vivi 1-19/+3
2015-11-24drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.Gravatar Rodrigo Vivi 1-3/+0
2015-11-18drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.Gravatar Rodrigo Vivi 1-4/+0
2015-11-18drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.Gravatar Rodrigo Vivi 1-1/+0
2015-11-18drm/i915: Reduce PSR re-activation time for VLV/CHV.Gravatar Rodrigo Vivi 1-2/+1
2015-11-18drm/i915: Delay first PSR activation.Gravatar Rodrigo Vivi 1-2/+16
2015-11-18drm/i915: Type safe register read/writeGravatar Ville Syrjälä 1-6/+6
2015-11-16drm/i915: Model PSR AUX register selection more like the normal AUX codeGravatar Ville Syrjälä 1-6/+21
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseGravatar Ville Syrjälä 1-12/+15
2015-11-16drm/i915: Parametrize AUX registersGravatar Ville Syrjälä 1-2/+3
2015-10-13drm/i915: Parametrize HSW video DIP data registersGravatar Ville Syrjälä 1-8/+10
2015-08-05drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.Gravatar Rodrigo Vivi 1-1/+2
2015-07-09drm/i915: PSR: Increase idle_framesGravatar Rodrigo Vivi 1-2/+5
2015-07-09drm/i915: PSR: Remove Low Power HW tracking mask.Gravatar Rodrigo Vivi 1-1/+1
2015-07-09drm/i915: PSR: Flush means invalidate + flushGravatar Rodrigo Vivi 1-19/+21
2015-06-24drm/i915/psr: Restrict single-shot updates to the PSR pipeGravatar Daniel Vetter 1-9/+13
2015-06-24drm/i915/psr: Restrict buffer tracking to the PSR pipeGravatar Daniel Vetter 1-4/+7
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