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path: root/drivers/irqchip/irq-sifive-plic.c
AgeCommit message (Expand)AuthorFilesLines
2020-11-01irqchip/sifive-plic: Fix chip_data access within a hierarchyGravatar Greentime Hu 1-4/+4
2020-10-25irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGravatar Greentime Hu 1-1/+1
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverGravatar Anup Patel 1-9/+23
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryGravatar Anup Patel 1-15/+1
2020-05-25irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesGravatar Anup Patel 1-2/+2
2020-05-25irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentGravatar Anup Patel 1-2/+12
2020-05-25irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Gravatar Anup Patel 1-0/+3
2020-05-18irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsGravatar Wesley W. Terpstra 1-2/+0
2020-04-17irqchip/sifive-plic: Fix maximum priority threshold valueGravatar Atish Patra 1-1/+1
2020-03-16irqchip/sifive-plic: Add support for multiple PLICsGravatar Atish Patra 1-30/+51
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineGravatar Atish Patra 1-4/+34
2020-01-24Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...Gravatar Thomas Gleixner 1-4/+26
2020-01-20irqchip/sifive-plic: Support irq domain hierarchyGravatar Yash Shah 1-4/+26
2020-01-04riscv: prefix IRQ_ macro names with an RV_ namespaceGravatar Paul Walmsley 1-1/+1
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeGravatar Christoph Hellwig 1-4/+7
2019-10-25Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...Gravatar Thomas Gleixner 1-2/+2
2019-10-25irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Gravatar Alan Mikhak 1-2/+2
2019-10-14Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...Gravatar Thomas Gleixner 1-14/+15
2019-09-18irqchip/sifive-plic: Switch to fasteoi flowGravatar Marc Zyngier 1-14/+15
2019-09-05irqchip/sifive-plic: set max threshold for ignored handlersGravatar Christoph Hellwig 1-2/+10
2019-02-21irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostGravatar Anup Patel 1-6/+39
2019-02-21irqchip/sifive-plic: Differentiate between PLIC handler and contextGravatar Anup Patel 1-8/+8
2019-02-21irqchip/sifive-plic: Add warning in plic_init() if handler already presentGravatar Anup Patel 1-0/+5
2019-02-21irqchip/sifive-plic: Pre-compute context hart base and enable baseGravatar Anup Patel 1-26/+21
2019-02-14irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.Gravatar Atish Patra 1-0/+5
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidGravatar Atish Patra 1-3/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidGravatar Palmer Dabbelt 1-1/+1
2018-08-13irqchip: add a SiFive PLIC driverGravatar Christoph Hellwig 1-0/+260