aboutsummaryrefslogtreecommitdiff
path: root/drivers/phy/cadence
AgeCommit message (Expand)AuthorFilesLines
2020-09-18phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configurationGravatar Swapnil Jakhade 1-0/+254
2020-09-18phy: cadence-torrent: Add PCIe + USB multilink configurationGravatar Swapnil Jakhade 1-0/+216
2020-09-18phy: cadence-torrent: Add single link USB register sequencesGravatar Swapnil Jakhade 1-1/+259
2020-09-18phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesGravatar Swapnil Jakhade 1-0/+89
2020-09-18phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsGravatar Swapnil Jakhade 1-4/+18
2020-09-18phy: cadence-torrent: Add PHY link configuration sequences for single linkGravatar Swapnil Jakhade 1-0/+44
2020-09-18phy: cadence-torrent: Add clk changes for multilink configurationGravatar Swapnil Jakhade 1-24/+17
2020-09-18phy: cadence-torrent: Update PHY reset for multilink configurationGravatar Swapnil Jakhade 1-7/+21
2020-09-18phy: cadence-torrent: Add support for PHY multilink configurationGravatar Swapnil Jakhade 1-26/+757
2020-09-18phy: cadence-torrent: Add PHY APB reset supportGravatar Swapnil Jakhade 1-0/+13
2020-09-18phy: cadence-torrent: Check cmn_ready assertion during PHY power onGravatar Swapnil Jakhade 1-1/+30
2020-09-18phy: cadence-torrent: Add single link PCIe supportGravatar Swapnil Jakhade 1-30/+266
2020-09-18phy: cadence-torrent: Check total lane count for all subnodes is within limitGravatar Swapnil Jakhade 1-4/+15
2020-09-18phy: cadence-torrent: Add separate regmap functions for torrent and DPGravatar Swapnil Jakhade 1-33/+66
2020-09-18phy: cadence-torrent: Enable support for multiple subnodesGravatar Swapnil Jakhade 1-15/+0
2020-09-18phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesGravatar Swapnil Jakhade 1-6/+2
2020-09-18phy: cadence-torrent: Use of_device_get_match_data() to get driver dataGravatar Swapnil Jakhade 1-8/+5
2020-09-16phy: cadence: torrent: Constify regmap_config structsGravatar Rikard Falkeborn 1-6/+6
2020-09-16phy: cadence: salvo: Constify cdns_nxp_sequence_pairGravatar Rikard Falkeborn 1-3/+3
2020-09-16phy: cadence: Sierra: Constify static structsGravatar Rikard Falkeborn 1-12/+12
2020-09-16Merge branch 'topic/phy_attrs' into nextGravatar Vinod Koul 1-0/+4
2020-09-16phy: cadence-torrent: Set Torrent PHY attributesGravatar Swapnil Jakhade 1-0/+4
2020-08-31phy: cadence: salvo: Constify cdns_salvo_phy_opsGravatar Rikard Falkeborn 1-1/+1
2020-07-13phy: cadence: salvo: fix wrong bit definitionGravatar Peter Chen 1-1/+1
2020-05-18phy: cadence: sierra: Fix for USB3 U1/U2 stateGravatar Sanket Parmar 1-13/+14
2020-05-15phy: phy-cadence-salvo: add phy .init APIGravatar Peter Chen 1-1/+11
2020-05-07phy: cadence: salvo: add salvo phy driverGravatar Peter Chen 3-0/+325
2020-03-20phy: cadence-torrent: Add support for subnode bindingsGravatar Swapnil Jakhade 1-75/+217
2020-03-20phy: cadence-torrent: Add platform dependent initialization structureGravatar Swapnil Jakhade 1-0/+9
2020-03-20phy: cadence-torrent: Use regmap to read and write DPTX PHY registersGravatar Swapnil Jakhade 1-69/+100
2020-03-20phy: cadence-torrent: Use regmap to read and write Torrent PHY registersGravatar Swapnil Jakhade 1-369/+650
2020-03-20phy: cadence-torrent: Implement PHY configure APIsGravatar Swapnil Jakhade 1-5/+431
2020-03-20phy: cadence-torrent: Add 19.2 MHz reference clock supportGravatar Swapnil Jakhade 1-17/+441
2020-03-20phy: cadence-torrent: Refactor code for reusabilityGravatar Swapnil Jakhade 1-93/+137
2020-03-20phy: cadence-torrent: Add wrapper for DPTX register accessGravatar Swapnil Jakhade 1-21/+50
2020-03-20phy: cadence-torrent: Add wrapper for PHY register accessGravatar Swapnil Jakhade 1-65/+77
2020-03-20phy: cadence-torrent: Adopt Torrent nomenclatureGravatar Swapnil Jakhade 1-53/+58
2020-03-20phy: cadence-dp: Rename to phy-cadence-torrentGravatar Yuti Amonkar 3-5/+5
2020-01-14phy: cadence: Sierra: add phy_reset hookGravatar Roger Quadros 1-0/+10
2020-01-14phy: cadence: Sierra: remove redundant initialization of pointer regmapGravatar Colin Ian King 1-1/+1
2020-01-08phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Gravatar Kishon Vijay Abraham I 1-1/+1
2020-01-08phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to...Gravatar Kishon Vijay Abraham I 1-0/+21
2020-01-08phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Gravatar Kishon Vijay Abraham I 1-1/+21
2020-01-08phy: cadence: Sierra: Check for PLL lock during PHY power onGravatar Kishon Vijay Abraham I 1-1/+32
2020-01-08phy: cadence: Sierra: Get reset control "array" for each linkGravatar Kishon Vijay Abraham I 1-1/+1
2020-01-08phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ex...Gravatar Anil Varughese 1-96/+254
2020-01-08phy: cadence: Sierra: Modify register macro names to be in sync with Sierra u...Gravatar Kishon Vijay Abraham I 1-83/+84
2020-01-08phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsGravatar Kishon Vijay Abraham I 1-6/+9
2020-01-08phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCGravatar Kishon Vijay Abraham I 1-0/+14
2020-01-08phy: cadence: Sierra: Use "regmap" for read and write to Sierra registersGravatar Kishon Vijay Abraham I 1-54/+237