aboutsummaryrefslogtreecommitdiff
path: root/drivers/phy/ti
AgeCommit message (Collapse)AuthorFilesLines
2024-04-12phy: ti: tusb1210: Resolve charger-det crash if charger psy is unregisteredGravatar Hans de Goede 1-11/+12
The power_supply frame-work is not really designed for there to be long living in kernel references to power_supply devices. Specifically unregistering a power_supply while some other code has a reference to it triggers a WARN in power_supply_unregister(): WARN_ON(atomic_dec_return(&psy->use_cnt)); Folllowed by the power_supply still getting removed and the backing data freed anyway, leaving the tusb1210 charger-detect code with a dangling reference, resulting in a crash the next time tusb1210_get_online() is called. Fix this by only holding the reference in tusb1210_get_online() freeing it at the end of the function. Note this still leaves a theoretical race window, but it avoids the issue when manually rmmod-ing the charger chip driver during development. Fixes: 48969a5623ed ("phy: ti: tusb1210: Add charger detection") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20240406140821.18624-1-hdegoede@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-03-16Merge tag 'phy-for-6.9' of ↵Gravatar Linus Torvalds 4-30/+57
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS PHY and SDM630 USBC support - Rockchip HDMI/eDP Combo PHY driver - Mediatek MT8365 CSI phy driver Updates: - Rework on Qualcomm phy PCS registers and type-c handling - Cadence torrent phy updates for multilink configuration - TI gmii resume support" * tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits) phy: constify of_phandle_args in xlate phy: ti: tusb1210: Define device IDs phy: ti: tusb1210: Use temporary variable for struct device phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema phy: ti: gmii-sel: add resume support phy: mtk-mipi-csi: add driver for CSI phy dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200 dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200 phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1 phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API dt-bindings: phy: qmp-ufs: Fix PHY clocks phy: qcom: sgmii-eth: move PCS registers to separate header phy: qcom: sgmii-eth: use existing register definitions phy: qcom: qmp-usbc: drop has_pwrdn_delay handling phy: qcom: qmp: move common bits definitions to common header phy: qcom: qmp: split DP PHY registers to separate headers ...
2024-02-23phy: constify of_phandle_args in xlateGravatar Krzysztof Kozlowski 3-3/+3
The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-16phy: ti: tusb1210: Define device IDsGravatar Andy Shevchenko 1-5/+7
Define device IDs since some of them are being used more than once. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240209160334.2304230-3-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-16phy: ti: tusb1210: Use temporary variable for struct deviceGravatar Andy Shevchenko 1-23/+24
Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240209160334.2304230-2-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-07phy: ti: gmii-sel: add resume supportGravatar Thomas Richard 1-0/+24
The resume callback restores the submode of each PHY. It uses the submode stored in struct phy_gmii_sel_phy_priv (variable phy_if_mode). The submode was saved by the set_mode PHY operation. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240125171754.773909-1-thomas.richard@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: ti: phy-omap-usb2: Fix NULL pointer dereference for SRPGravatar Tony Lindgren 1-2/+2
If the external phy working together with phy-omap-usb2 does not implement send_srp(), we may still attempt to call it. This can happen on an idle Ethernet gadget triggering a wakeup for example: configfs-gadget.g1 gadget.0: ECM Suspend configfs-gadget.g1 gadget.0: Port suspended. Triggering wakeup ... Unable to handle kernel NULL pointer dereference at virtual address 00000000 when execute ... PC is at 0x0 LR is at musb_gadget_wakeup+0x1d4/0x254 [musb_hdrc] ... musb_gadget_wakeup [musb_hdrc] from usb_gadget_wakeup+0x1c/0x3c [udc_core] usb_gadget_wakeup [udc_core] from eth_start_xmit+0x3b0/0x3d4 [u_ether] eth_start_xmit [u_ether] from dev_hard_start_xmit+0x94/0x24c dev_hard_start_xmit from sch_direct_xmit+0x104/0x2e4 sch_direct_xmit from __dev_queue_xmit+0x334/0xd88 __dev_queue_xmit from arp_solicit+0xf0/0x268 arp_solicit from neigh_probe+0x54/0x7c neigh_probe from __neigh_event_send+0x22c/0x47c __neigh_event_send from neigh_resolve_output+0x14c/0x1c0 neigh_resolve_output from ip_finish_output2+0x1c8/0x628 ip_finish_output2 from ip_send_skb+0x40/0xd8 ip_send_skb from udp_send_skb+0x124/0x340 udp_send_skb from udp_sendmsg+0x780/0x984 udp_sendmsg from __sys_sendto+0xd8/0x158 __sys_sendto from ret_fast_syscall+0x0/0x58 Let's fix the issue by checking for send_srp() and set_vbus() before calling them. For USB peripheral only cases these both could be NULL. Fixes: 657b306a7bdf ("usb: phy: add a new driver for omap usb2 phy") Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20240128120556.8848-1-tony@atomide.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-18Merge tag 'phy-for-6.8' of ↵Gravatar Linus Torvalds 2-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Qualcomm SM8650 UFS, PCIe and USB/DP Combo PHY, eUSB2 PHY, SDX75 USB3, X1E80100 USB3 support - Mediatek MT8195 support - Rockchip RK3128 usb2 support - TI SGMII mode for J784S4 Updates: - Qualcomm v7 register offsets updates - Mediatek tphy support for force phy mode switch" * tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (34 commits) phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4 phy: ti: gmii-sel: Enable SGMII mode for J784S4 phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible phy: mediatek: tphy: add support force phy mode switch dt-bindings: phy: mediatek: tphy: add a property for force-mode switch phy: phy-can-transceiver: insert space after include phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY phy: qcom-qmp: qserdes-txrx: Add v7 register offsets phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets phy: qcom-qmp: qserdes-com: Add v7 register offsets phy: qcom-qmp: pcs-usb: Add v7 register offsets phy: qcom-qmp: pcs: Add v7 register offsets phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets phy: qcom-qmp: qserdes-com: Add some more v6 register offsets ...
2023-12-22phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4Gravatar Chintan Vankar 1-0/+1
Enable full rate divider configuration support for J784S4_WIZ_10G for SGMII. Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20231221102956.754617-2-c-vankar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-22phy: ti: gmii-sel: Enable SGMII mode for J784S4Gravatar Chintan Vankar 1-1/+1
TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20231221102956.754617-1-c-vankar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16phy: ti: gmii-sel: Fix register offset when parent is not a syscon nodeGravatar Andrew Davis 1-1/+4
When the node for this phy selector is a child node of a syscon node then the property 'reg' is used as an offset into the parent regmap. When the node is standalone and gets its own regmap this offset is pre-applied. So we need to track which method was used to get the regmap and not apply the offset in the standalone case. Fixes: 1fdfa7cccd35 ("phy: ti: gmii-sel: Allow parent to not be syscon node") Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20231025143302.1265633-1-afd@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13phy: Drop unnecessary of_match_device() callsGravatar Rob Herring 1-10/+1
If probe is reached, we've already matched the device and in the case of DT matching, the struct device_node pointer will be set. Therefore, there is no need to call of_match_device() in probe. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231009172923.2457844-16-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13phy: Use device_get_match_data()Gravatar Rob Herring 3-24/+10
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231009172923.2457844-15-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-17phy: Explicitly include correct DT includesGravatar Rob Herring 2-0/+2
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-14phy: ti: gmii-sel: Allow parent to not be syscon nodeGravatar Andrew Davis 1-3/+6
If the parent node is not a syscon type, then fallback and check if we can get a regmap from our own node. This no longer forces us to make the parent of this node a syscon node when that might not be appropriate. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20230713200957.134480-1-afd@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-05Merge tag 'phy-for-6.5_v2' of ↵Gravatar Linus Torvalds 1-2/+32
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Debugfs support for phy core and mediatek driver - Hisilicon inno-usb2-phy driver supporting Hi3798MV100 - Qualcomm SGMII SerDes PHY driver, SM6115 & QCM2290 QMP-USB support, SA8775P USB PHY & USB3 UNI support, QUSB2 support for IPQ9574, IPQ9574 USB3 PHY UpdatesL - Sparx5 serdes phy power optimzation - cadence salvo usb properties and updates and torrent DP with PCIe & USB support - Yaml conversion for Broadcom kona USB bindings and MXS USB binding" * tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (67 commits) dt-bindings: phy: brcm,brcmstb-usb-phy: Fix error in "compatible" conditional schema dt-bindings: phy: mixel,mipi-dsi-phy: Remove assigned-clock* properties dt-bindings: phy: intel,combo-phy: restrict node name suffixes dt-bindings: phy: qcom,usb-hs-phy: Add compatible phy: tegra: xusb: check return value of devm_kzalloc() phy: qcom: qmp-combo: fix Display Port PHY configuration for SM8550 phy: qcom: add the SGMII SerDes PHY driver dt-bindings: phy: describe the Qualcomm SGMII PHY phy: qualcomm: fix indentation in Makefile phy: usb: suppress OC condition for 7439b2 phy: usb: Turn off phy when port is in suspend phy: tegra: xusb: Clear the driver reference in usb-phy dev dt-bindings: phy: mxs-usb-phy: add imx8ulp and imx8qm compatible dt-bindings: phy: mxs-usb-phy: convert to DT schema format dt-bindings: phy: qcom,qmp-usb: fix bindings error dt-bindings: phy: qcom,qmp-ufs: fix the sc8180x regs dt-bindings: phy: qcom,qmp-pcie: fix the sc8180x regs phy: mediatek: tphy: add debugfs files phy: core: add debugfs files phy: fsl-imx8mp-usb: add support for phy tuning ...
2023-06-08phy: ti: j721e-wiz: Add a determine_rate hookGravatar Maxime Ripard 1-0/+1
The TI J721e Wiz clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-44-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-06-08phy: ti: am654-serdes: Add a determine_rate hookGravatar Maxime Ripard 1-0/+1
The TI AM654 SerDes clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-43-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-05-16phy: ti: gmii-sel: Enable USXGMII mode for J784S4Gravatar Siddharth Vadapalli 1-1/+10
TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4Gravatar Siddharth Vadapalli 1-0/+13
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Enable SGMII mode for J721EGravatar Siddharth Vadapalli 1-1/+1
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Enable SGMII mode for J7200Gravatar Siddharth Vadapalli 1-1/+1
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Add support for SGMII modeGravatar Siddharth Vadapalli 1-0/+8
Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC supports it. The extra_modes member of the phy_gmii_sel_soc_data struct corresponding to the SoC is used to determine whether or not the SoC supports SGMII mode. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-04-12phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721EGravatar Siddharth Vadapalli 1-0/+2
Enable full rate divider configuration support for J721E_WIZ_16G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309092434.443550-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-04-12phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()Gravatar Siddharth Vadapalli 1-6/+5
In the wiz_mode_select() function, the configuration performed for PHY_TYPE_USXGMII is unreachable. Fix it. Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230403094552.929108-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-31phy: omap-usb2-phy: Use dev_err_probe()Gravatar Ye Xingchen 1-5/+3
Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/202303231545522162256@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-twl4030-usb: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-32-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-ti-pipe3: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-31-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-omap-usb2: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-30-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-j721e-wiz: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-29-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-dm816x-usb: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-28-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-da8xx-usb: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-27-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: ti: phy-am654-serdes: Convert to platform remove callback returning voidGravatar Uwe Kleine-König 1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-26-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-14Merge tag 'phy-fixes-6.2' into nextGravatar Vinod Koul 1-2/+2
Merge fixes tag pulled into mainline by Linus into phy/next due to dependency on amlogic patches
2023-01-18phy: ti: j721e-wiz: Add support to enable LN23 Type-C swapGravatar Sinthu Raja 1-5/+33
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230113150615.19375-3-sinthu.raja@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specifiedGravatar Sinthu Raja 1-10/+28
It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-dir-gpios property. Add code to handle LN10 Type-C swap if typec-dir-gpios property is not specified in DT. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230113150615.19375-2-sinthu.raja@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-11phy: ti: fix Kconfig warning and operator precedenceGravatar Randy Dunlap 1-2/+2
Fix Kconfig depends operator precedence to prevent a Kconfig warning: WARNING: unmet direct dependencies detected for MUX_MMIO Depends on [n]: MULTIPLEXER [=m] && OF [=n] Selected by [m]: - PHY_AM654_SERDES [=m] && (OF [=n] && ARCH_K3 || COMPILE_TEST [=y]) && COMMON_CLK [=y] Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC") Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: linux-phy@lists.infradead.org Cc: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230110062529.22668-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-24phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module supportGravatar Matt Ranostay 1-0/+16
Add support for j721s2-wiz-10g device which is similar to j721e-wiz-10g but uses clock-names interface versus explicitly defining clock nodes within device tree node. Signed-off-by: Matt Ranostay <mranostay@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20221123032413.1193961-3-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-07phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721eGravatar Siddharth Vadapalli 1-0/+13
Each of the CPSW9G ports in J721e support additional modes like QSGMII. Add a new compatible for J721e to support the additional modes. In TI's J721e, each of the CPSW9G ethernet interfaces can act as a QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20221026074532.109220-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-07phy: ti: gmii-sel: Update methods for fetching and using qsgmii main portGravatar Siddharth Vadapalli 1-7/+22
The number of QSGMII main ports are specific to the device. TI's J7200 for which the QSGMII main port property is fetched from the device-tree has only one QSGMII main port. However, devices like TI's J721e support up to two QSGMII main ports. Thus, the existing methods for fetching and using the QSGMII main port are not scalable. Update the existing methods for handling the QSGMII main ports and its associated requirements to make it scalable for future devices. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20221026074532.109220-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-17phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module supportGravatar Matt Ranostay 1-0/+22
Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Acked-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20221015201123.195477-3-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-24phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe()Gravatar Dan Carpenter 1-2/+3
These two error paths need to call of_node_put(child_node) before returning. Fixes: edd473d4293a ("phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g") Fixes: 7ae14cf581f2 ("phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/YyxFI8aW23IC/21U@kili Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-20phy: ti: phy-j721e-wiz: stop name conflict if multiple serdes are initializedGravatar Matt Ranostay 1-1/+14
When multiple serdes instances are initialized the first will succeed but additional will conflict over clocks names and probing fails. Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220909200026.3422-1-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-13phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200Gravatar Siddharth Vadapalli 1-3/+44
Each of the CPSW5G ports in J7200 support additional modes like QSGMII. Add a new compatible for J7200 to support the additional modes. In TI's J7200, each of the CPSW5G ethernet interfaces can act as a QSGMII or QSGMII-SUB port. The QSGMII interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. To indicate the interface which will serve as the main QSGMII interface, add a property "ti,qsgmii-main-ports", whose value indicates the port number of the interface which shall serve as the main QSGMII interface. The rest of the interfaces are then assigned QSGMII-SUB mode by default. The property "ti,qsgmii-main-ports" is used to configure the CTRLMMR_ENETx_CTRL register. Depending on the device, it is possible for more than one QSGMII main port to exist. Thus, the property "ti,qsgmii-main-ports" is defined as an array of values in order to reuse the property for other devices. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20220912085650.83263-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-08-30phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rateGravatar Roger Quadros 1-0/+24
For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-08-30phy: ti: phy-j721e-wiz: add support for j7200-wiz-10gGravatar Roger Quadros 1-9/+129
j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-7-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-08-30phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driverGravatar Tanmay Patil 1-1/+50
Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by: Tanmay Patil <t-patil@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-4-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-08-30phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200Gravatar Siddharth Vadapalli 1-6/+13
Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-2-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-08-04Merge tag 'spdx-6.0-rc1' of ↵Gravatar Linus Torvalds 1-10/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx Pull SPDX updates from Greg KH: "Here is the set of SPDX comment updates for 6.0-rc1. Nothing huge here, just a number of updated SPDX license tags and cleanups based on the review of a number of common patterns in GPLv2 boilerplate text. Also included in here are a few other minor updates, two USB files, and one Documentation file update to get the SPDX lines correct. All of these have been in the linux-next tree for a very long time" * tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits) Documentation: samsung-s3c24xx: Add blank line after SPDX directive x86/crypto: Remove stray comment terminator treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE ...
2022-07-05phy: ti: tusb1210: Don't check for write errors when powering onGravatar Andy Shevchenko 1-2/+3
On some platforms, like Intel Merrifield, the writing values during power on may timeout: tusb1210 dwc3.0.auto.ulpi: error -110 writing val 0x41 to reg 0x80 phy phy-dwc3.0.auto.ulpi.0: phy poweron failed --> -110 dwc3 dwc3.0.auto: error -ETIMEDOUT: failed to initialize core dwc3: probe of dwc3.0.auto failed with error -110 which effectively fails the probe of the USB controller. Drop the check as it was before the culprit commit (see Fixes tag). Fixes: 09a3512681b3 ("phy: ti: tusb1210: Improve ulpi_read()/_write() error checking") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Ferry Toth <fntoth@gmail.com> Link: https://lore.kernel.org/r/20220613160848.82746-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Copyright © 1990 – 2022 jet tsang zeon-git.
All Rights Reverse Engineered.